Printed circuit board with aligned connections and method of making same
The present invention provides an improved circuit board for mounting integrated circuit chips and a technique for manufacturing the circuit board. The board permits direct chip attachment to the circuit board by providing the necessary geometry for the footprint pattern of the chip connections with...
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creator | BOYKO CHRISTINA M CARPENTER RICHARD W MARKOVICH VOYA R MAYO DARLEEN SABIA JOSEPH G BUCEK FRANCIS J REIDSEMA CINDY M |
description | The present invention provides an improved circuit board for mounting integrated circuit chips and a technique for manufacturing the circuit board. The board permits direct chip attachment to the circuit board by providing the necessary geometry for the footprint pattern of the chip connections without the necessity of multi-level packaging using chip carriers. The circuit board includes a substrate with plated through holes, and a film of photoresist dielectric material disposed on the substrate. The dielectric material is photo patterned to form vias which are then filled with conductive material. Electrical connection pads are formed on the exposed surface of the film of dielectric material in the pattern of the chip footprint to be mounted thereon. The vias and plated through holes are arranged in groups and patterns which provide some direct connection between the pads and plated through holes, some pads wired to vias on the exposed surface of the film of dielectric material and some vias wired to plated through holes on the surface of the substrate. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US5450290A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US5450290A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US5450290A3</originalsourceid><addsrcrecordid>eNrjZPAIKMrMK0lNUUjOLEouzSxRSMpPLEpRKM8syVBIzMlMzwNJ5eflpSaXZObnFSsk5qUo5KaWZOSnKOSnKeQmZmfmpSsUJ-am8jCwpiXmFKfyQmluBnk31xBnD93Ugvz41OKCxOTUvNSS-NBgUxNTAyNLA0djwioA0PUzdQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Printed circuit board with aligned connections and method of making same</title><source>esp@cenet</source><creator>BOYKO; CHRISTINA M ; CARPENTER; RICHARD W ; MARKOVICH; VOYA R ; MAYO; DARLEEN ; SABIA; JOSEPH G ; BUCEK; FRANCIS J ; REIDSEMA; CINDY M</creator><creatorcontrib>BOYKO; CHRISTINA M ; CARPENTER; RICHARD W ; MARKOVICH; VOYA R ; MAYO; DARLEEN ; SABIA; JOSEPH G ; BUCEK; FRANCIS J ; REIDSEMA; CINDY M</creatorcontrib><description>The present invention provides an improved circuit board for mounting integrated circuit chips and a technique for manufacturing the circuit board. The board permits direct chip attachment to the circuit board by providing the necessary geometry for the footprint pattern of the chip connections without the necessity of multi-level packaging using chip carriers. The circuit board includes a substrate with plated through holes, and a film of photoresist dielectric material disposed on the substrate. The dielectric material is photo patterned to form vias which are then filled with conductive material. Electrical connection pads are formed on the exposed surface of the film of dielectric material in the pattern of the chip footprint to be mounted thereon. The vias and plated through holes are arranged in groups and patterns which provide some direct connection between the pads and plated through holes, some pads wired to vias on the exposed surface of the film of dielectric material and some vias wired to plated through holes on the surface of the substrate.</description><edition>6</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CABLES ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; CONDUCTORS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INSULATORS ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES ; SEMICONDUCTOR DEVICES</subject><creationdate>1995</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19950912&DB=EPODOC&CC=US&NR=5450290A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76294</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19950912&DB=EPODOC&CC=US&NR=5450290A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BOYKO; CHRISTINA M</creatorcontrib><creatorcontrib>CARPENTER; RICHARD W</creatorcontrib><creatorcontrib>MARKOVICH; VOYA R</creatorcontrib><creatorcontrib>MAYO; DARLEEN</creatorcontrib><creatorcontrib>SABIA; JOSEPH G</creatorcontrib><creatorcontrib>BUCEK; FRANCIS J</creatorcontrib><creatorcontrib>REIDSEMA; CINDY M</creatorcontrib><title>Printed circuit board with aligned connections and method of making same</title><description>The present invention provides an improved circuit board for mounting integrated circuit chips and a technique for manufacturing the circuit board. The board permits direct chip attachment to the circuit board by providing the necessary geometry for the footprint pattern of the chip connections without the necessity of multi-level packaging using chip carriers. The circuit board includes a substrate with plated through holes, and a film of photoresist dielectric material disposed on the substrate. The dielectric material is photo patterned to form vias which are then filled with conductive material. Electrical connection pads are formed on the exposed surface of the film of dielectric material in the pattern of the chip footprint to be mounted thereon. The vias and plated through holes are arranged in groups and patterns which provide some direct connection between the pads and plated through holes, some pads wired to vias on the exposed surface of the film of dielectric material and some vias wired to plated through holes on the surface of the substrate.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CABLES</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>CONDUCTORS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INSULATORS</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1995</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPAIKMrMK0lNUUjOLEouzSxRSMpPLEpRKM8syVBIzMlMzwNJ5eflpSaXZObnFSsk5qUo5KaWZOSnKOSnKeQmZmfmpSsUJ-am8jCwpiXmFKfyQmluBnk31xBnD93Ugvz41OKCxOTUvNSS-NBgUxNTAyNLA0djwioA0PUzdQ</recordid><startdate>19950912</startdate><enddate>19950912</enddate><creator>BOYKO; CHRISTINA M</creator><creator>CARPENTER; RICHARD W</creator><creator>MARKOVICH; VOYA R</creator><creator>MAYO; DARLEEN</creator><creator>SABIA; JOSEPH G</creator><creator>BUCEK; FRANCIS J</creator><creator>REIDSEMA; CINDY M</creator><scope>EVB</scope></search><sort><creationdate>19950912</creationdate><title>Printed circuit board with aligned connections and method of making same</title><author>BOYKO; CHRISTINA M ; CARPENTER; RICHARD W ; MARKOVICH; VOYA R ; MAYO; DARLEEN ; SABIA; JOSEPH G ; BUCEK; FRANCIS J ; REIDSEMA; CINDY M</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5450290A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1995</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CABLES</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>CONDUCTORS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INSULATORS</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>BOYKO; CHRISTINA M</creatorcontrib><creatorcontrib>CARPENTER; RICHARD W</creatorcontrib><creatorcontrib>MARKOVICH; VOYA R</creatorcontrib><creatorcontrib>MAYO; DARLEEN</creatorcontrib><creatorcontrib>SABIA; JOSEPH G</creatorcontrib><creatorcontrib>BUCEK; FRANCIS J</creatorcontrib><creatorcontrib>REIDSEMA; CINDY M</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BOYKO; CHRISTINA M</au><au>CARPENTER; RICHARD W</au><au>MARKOVICH; VOYA R</au><au>MAYO; DARLEEN</au><au>SABIA; JOSEPH G</au><au>BUCEK; FRANCIS J</au><au>REIDSEMA; CINDY M</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Printed circuit board with aligned connections and method of making same</title><date>1995-09-12</date><risdate>1995</risdate><abstract>The present invention provides an improved circuit board for mounting integrated circuit chips and a technique for manufacturing the circuit board. The board permits direct chip attachment to the circuit board by providing the necessary geometry for the footprint pattern of the chip connections without the necessity of multi-level packaging using chip carriers. The circuit board includes a substrate with plated through holes, and a film of photoresist dielectric material disposed on the substrate. The dielectric material is photo patterned to form vias which are then filled with conductive material. Electrical connection pads are formed on the exposed surface of the film of dielectric material in the pattern of the chip footprint to be mounted thereon. The vias and plated through holes are arranged in groups and patterns which provide some direct connection between the pads and plated through holes, some pads wired to vias on the exposed surface of the film of dielectric material and some vias wired to plated through holes on the surface of the substrate.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS CABLES CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS CONDUCTORS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY INSULATORS MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES SEMICONDUCTOR DEVICES |
title | Printed circuit board with aligned connections and method of making same |
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