Fast content addressable memory with reduced power consumption

Fast content addressable memory with reduced power consumption

A content addressable memory in accordance with the present invention includes a number of bistable memory cells having as inputs thereto first and second bit lines and an address line, and a COMPARE circuit connected to each of the memory cells so as to provide the COMPARE function without loading...

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Hauptverfasser: NUECHTERLEIN, DAVID W, ATALLAH, FRANCOIS I, GARVIN, STACY J
Format: Patent
Sprache:eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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creator NUECHTERLEIN
DAVID W
ATALLAH
FRANCOIS I
GARVIN
STACY J
description A content addressable memory in accordance with the present invention includes a number of bistable memory cells having as inputs thereto first and second bit lines and an address line, and a COMPARE circuit connected to each of the memory cells so as to provide the COMPARE function without loading the first and second bit lines and including means for inhibiting current flow when a miscompare occurs.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US5396449A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US5396449A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US5396449A3</originalsourceid><addsrcrecordid>eNrjZLBzSywuUUjOzytJzStRSExJKUotLk5MyklVyE3NzS-qVCjPLMlQKEpNKU1OTVEoyC9PLQKpLi7NLSjJzM_jYWBNS8wpTuWF0twM8m6uIc4euqkF-fGpxQWJyal5qSXxocGmxpZmJiaWjsaEVQAA37Ewnw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Fast content addressable memory with reduced power consumption</title><source>esp@cenet</source><creator>NUECHTERLEIN; DAVID W ; ATALLAH; FRANCOIS I ; GARVIN; STACY J</creator><creatorcontrib>NUECHTERLEIN; DAVID W ; ATALLAH; FRANCOIS I ; GARVIN; STACY J</creatorcontrib><description>A content addressable memory in accordance with the present invention includes a number of bistable memory cells having as inputs thereto first and second bit lines and an address line, and a COMPARE circuit connected to each of the memory cells so as to provide the COMPARE function without loading the first and second bit lines and including means for inhibiting current flow when a miscompare occurs.</description><edition>6</edition><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>1995</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19950307&amp;DB=EPODOC&amp;CC=US&amp;NR=5396449A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19950307&amp;DB=EPODOC&amp;CC=US&amp;NR=5396449A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NUECHTERLEIN; DAVID W</creatorcontrib><creatorcontrib>ATALLAH; FRANCOIS I</creatorcontrib><creatorcontrib>GARVIN; STACY J</creatorcontrib><title>Fast content addressable memory with reduced power consumption</title><description>A content addressable memory in accordance with the present invention includes a number of bistable memory cells having as inputs thereto first and second bit lines and an address line, and a COMPARE circuit connected to each of the memory cells so as to provide the COMPARE function without loading the first and second bit lines and including means for inhibiting current flow when a miscompare occurs.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1995</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLBzSywuUUjOzytJzStRSExJKUotLk5MyklVyE3NzS-qVCjPLMlQKEpNKU1OTVEoyC9PLQKpLi7NLSjJzM_jYWBNS8wpTuWF0twM8m6uIc4euqkF-fGpxQWJyal5qSXxocGmxpZmJiaWjsaEVQAA37Ewnw</recordid><startdate>19950307</startdate><enddate>19950307</enddate><creator>NUECHTERLEIN; DAVID W</creator><creator>ATALLAH; FRANCOIS I</creator><creator>GARVIN; STACY J</creator><scope>EVB</scope></search><sort><creationdate>19950307</creationdate><title>Fast content addressable memory with reduced power consumption</title><author>NUECHTERLEIN; DAVID W ; ATALLAH; FRANCOIS I ; GARVIN; STACY J</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5396449A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1995</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>NUECHTERLEIN; DAVID W</creatorcontrib><creatorcontrib>ATALLAH; FRANCOIS I</creatorcontrib><creatorcontrib>GARVIN; STACY J</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NUECHTERLEIN; DAVID W</au><au>ATALLAH; FRANCOIS I</au><au>GARVIN; STACY J</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Fast content addressable memory with reduced power consumption</title><date>1995-03-07</date><risdate>1995</risdate><abstract>A content addressable memory in accordance with the present invention includes a number of bistable memory cells having as inputs thereto first and second bit lines and an address line, and a COMPARE circuit connected to each of the memory cells so as to provide the COMPARE function without loading the first and second bit lines and including means for inhibiting current flow when a miscompare occurs.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record>
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PHYSICS
STATIC STORES
title Fast content addressable memory with reduced power consumption
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-30T11%3A10%3A02IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NUECHTERLEIN;%20DAVID%20W&rft.date=1995-03-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS5396449A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true