Nonvolatile memory array wordline driver circuit with voltage translator circuit
A circuit for driving a wordline or group of wordlines in a floating-gate type EEPROM cell array includes a read-driver subcircuit for switching positive read voltages, a program-driver subcircuit for switching positive programming voltages and, optionally, a subcircuit for switching negative erasin...
Gespeichert in:
Hauptverfasser: | , , , , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | A circuit for driving a wordline or group of wordlines in a floating-gate type EEPROM cell array includes a read-driver subcircuit for switching positive read voltages, a program-driver subcircuit for switching positive programming voltages and, optionally, a subcircuit for switching negative erasing voltages. The read-driver subcircuit may be constructed using relatively short-channel transistors for relatively high speed operation when connected to high-capacitance wordlines. On the other hand, the program-driver subcircuit may be constructed using relatively long-channel transistors and those long-channel transistors may be located on the memory chip remotely from the memory cells and from the read-driver circuit. P channel isolating transistors are used to isolate unused circuitry during operation. A voltage translator in the program-driver subcircuit has a transistor configuration that lessens the probability that the breakdown voltages of those transistors will be exceeded. A method for programming nonvolatile memory cell arrays is also disclosed. |
---|