Via paste compositions and use thereof to form conductive vias in circuitized ceramic substrates
Improved via-filling compositions for producing conductive vias in circuitized ceramic substrates, particularly multilayer substrates, without cracking and/or loss of hermetic sealing. The via-filling compositions comprise pastes containing a mixture of (a) ceramic and/or glass spheres of substantia...
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creator | VAN HISE JON A FAROOQ SHAJI MULLER-LANDAU FRIEDEL GIESS EDWARD A DUNCOMBE PETER R VALLABHANENI RAO SHAW ROBERT R WALKER GEORGE F BROWNLOW, DECEASED JAMES M KIM YOUNG-HO AOUDE FARID Y NEISSER MARK O PARK JAE M KIM JUNGIHL RITA ROBERT A KNICKERBOCKER SARAH H SHAW THOMAS M COOPER EMANUEL I |
description | Improved via-filling compositions for producing conductive vias in circuitized ceramic substrates, particularly multilayer substrates, without cracking and/or loss of hermetic sealing. The via-filling compositions comprise pastes containing a mixture of (a) ceramic and/or glass spheres of substantially- uniform diameter between about 0.5 and 6 (my)m, (b) conductive metal particles or spheres having a maximum dimension or diameter between about 1/3 and 1/4 of the diameter of the ceramic and/or glass spheres, and (c) a binder vehicle. The formed conductive via bodies comprise a uniform conductive skeletal network of sintered metal particles densely packed within a uniform matrix of the co-sintered ceramic and/or glass spheres, which matrix is hermetically fused and integrated with ceramic layers forming the wall of the via in the ceramic circuit substrate. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US5283104A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US5283104A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US5283104A3</originalsourceid><addsrcrecordid>eNqFyz0OwjAMQOEuDAg4A74AElCQWBECsfOzFuO6whKJo9jpwOnpwM70lu-Nq8ddEBKaM5CGpCYuGg0wtlCMwV-cWTtwhU5zGFBsC7n0DL2ggUQgyVSG7cMtEGcMQmDlaZ7R2abVqMO38ezXSTU_Ha-H84KTNmwJiSN7c7ts17t6tdzs6__iCwuMPSg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Via paste compositions and use thereof to form conductive vias in circuitized ceramic substrates</title><source>esp@cenet</source><creator>VAN HISE; JON A ; FAROOQ; SHAJI ; MULLER-LANDAU; FRIEDEL ; GIESS; EDWARD A ; DUNCOMBE; PETER R ; VALLABHANENI; RAO ; SHAW; ROBERT R ; WALKER; GEORGE F ; BROWNLOW, DECEASED; JAMES M ; KIM; YOUNG-HO ; AOUDE; FARID Y ; NEISSER; MARK O ; PARK; JAE M ; KIM; JUNGIHL ; RITA; ROBERT A ; KNICKERBOCKER; SARAH H ; SHAW; THOMAS M ; COOPER; EMANUEL I</creator><creatorcontrib>VAN HISE; JON A ; FAROOQ; SHAJI ; MULLER-LANDAU; FRIEDEL ; GIESS; EDWARD A ; DUNCOMBE; PETER R ; VALLABHANENI; RAO ; SHAW; ROBERT R ; WALKER; GEORGE F ; BROWNLOW, DECEASED; JAMES M ; KIM; YOUNG-HO ; AOUDE; FARID Y ; NEISSER; MARK O ; PARK; JAE M ; KIM; JUNGIHL ; RITA; ROBERT A ; KNICKERBOCKER; SARAH H ; SHAW; THOMAS M ; COOPER; EMANUEL I</creatorcontrib><description>Improved via-filling compositions for producing conductive vias in circuitized ceramic substrates, particularly multilayer substrates, without cracking and/or loss of hermetic sealing. The via-filling compositions comprise pastes containing a mixture of (a) ceramic and/or glass spheres of substantially- uniform diameter between about 0.5 and 6 (my)m, (b) conductive metal particles or spheres having a maximum dimension or diameter between about 1/3 and 1/4 of the diameter of the ceramic and/or glass spheres, and (c) a binder vehicle. The formed conductive via bodies comprise a uniform conductive skeletal network of sintered metal particles densely packed within a uniform matrix of the co-sintered ceramic and/or glass spheres, which matrix is hermetically fused and integrated with ceramic layers forming the wall of the via in the ceramic circuit substrate.</description><edition>5</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CABLES ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; CONDUCTORS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC ; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS ; INSULATORS ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES ; SEMICONDUCTOR DEVICES ; TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ; TECHNICAL SUBJECTS COVERED BY FORMER USPC ; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS ; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS</subject><creationdate>1994</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940201&DB=EPODOC&CC=US&NR=5283104A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940201&DB=EPODOC&CC=US&NR=5283104A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>VAN HISE; JON A</creatorcontrib><creatorcontrib>FAROOQ; SHAJI</creatorcontrib><creatorcontrib>MULLER-LANDAU; FRIEDEL</creatorcontrib><creatorcontrib>GIESS; EDWARD A</creatorcontrib><creatorcontrib>DUNCOMBE; PETER R</creatorcontrib><creatorcontrib>VALLABHANENI; RAO</creatorcontrib><creatorcontrib>SHAW; ROBERT R</creatorcontrib><creatorcontrib>WALKER; GEORGE F</creatorcontrib><creatorcontrib>BROWNLOW, DECEASED; JAMES M</creatorcontrib><creatorcontrib>KIM; YOUNG-HO</creatorcontrib><creatorcontrib>AOUDE; FARID Y</creatorcontrib><creatorcontrib>NEISSER; MARK O</creatorcontrib><creatorcontrib>PARK; JAE M</creatorcontrib><creatorcontrib>KIM; JUNGIHL</creatorcontrib><creatorcontrib>RITA; ROBERT A</creatorcontrib><creatorcontrib>KNICKERBOCKER; SARAH H</creatorcontrib><creatorcontrib>SHAW; THOMAS M</creatorcontrib><creatorcontrib>COOPER; EMANUEL I</creatorcontrib><title>Via paste compositions and use thereof to form conductive vias in circuitized ceramic substrates</title><description>Improved via-filling compositions for producing conductive vias in circuitized ceramic substrates, particularly multilayer substrates, without cracking and/or loss of hermetic sealing. The via-filling compositions comprise pastes containing a mixture of (a) ceramic and/or glass spheres of substantially- uniform diameter between about 0.5 and 6 (my)m, (b) conductive metal particles or spheres having a maximum dimension or diameter between about 1/3 and 1/4 of the diameter of the ceramic and/or glass spheres, and (c) a binder vehicle. The formed conductive via bodies comprise a uniform conductive skeletal network of sintered metal particles densely packed within a uniform matrix of the co-sintered ceramic and/or glass spheres, which matrix is hermetically fused and integrated with ceramic layers forming the wall of the via in the ceramic circuit substrate.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CABLES</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>CONDUCTORS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</subject><subject>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</subject><subject>INSULATORS</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1994</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqFyz0OwjAMQOEuDAg4A74AElCQWBECsfOzFuO6whKJo9jpwOnpwM70lu-Nq8ddEBKaM5CGpCYuGg0wtlCMwV-cWTtwhU5zGFBsC7n0DL2ggUQgyVSG7cMtEGcMQmDlaZ7R2abVqMO38ezXSTU_Ha-H84KTNmwJiSN7c7ts17t6tdzs6__iCwuMPSg</recordid><startdate>19940201</startdate><enddate>19940201</enddate><creator>VAN HISE; JON A</creator><creator>FAROOQ; SHAJI</creator><creator>MULLER-LANDAU; FRIEDEL</creator><creator>GIESS; EDWARD A</creator><creator>DUNCOMBE; PETER R</creator><creator>VALLABHANENI; RAO</creator><creator>SHAW; ROBERT R</creator><creator>WALKER; GEORGE F</creator><creator>BROWNLOW, DECEASED; JAMES M</creator><creator>KIM; YOUNG-HO</creator><creator>AOUDE; FARID Y</creator><creator>NEISSER; MARK O</creator><creator>PARK; JAE M</creator><creator>KIM; JUNGIHL</creator><creator>RITA; ROBERT A</creator><creator>KNICKERBOCKER; SARAH H</creator><creator>SHAW; THOMAS M</creator><creator>COOPER; EMANUEL I</creator><scope>EVB</scope></search><sort><creationdate>19940201</creationdate><title>Via paste compositions and use thereof to form conductive vias in circuitized ceramic substrates</title><author>VAN HISE; JON A ; FAROOQ; SHAJI ; MULLER-LANDAU; FRIEDEL ; GIESS; EDWARD A ; DUNCOMBE; PETER R ; VALLABHANENI; RAO ; SHAW; ROBERT R ; WALKER; GEORGE F ; BROWNLOW, DECEASED; JAMES M ; KIM; YOUNG-HO ; AOUDE; FARID Y ; NEISSER; MARK O ; PARK; JAE M ; KIM; JUNGIHL ; RITA; ROBERT A ; KNICKERBOCKER; SARAH H ; SHAW; THOMAS M ; COOPER; EMANUEL I</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5283104A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1994</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CABLES</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>CONDUCTORS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</topic><topic>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</topic><topic>INSULATORS</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS</topic><toplevel>online_resources</toplevel><creatorcontrib>VAN HISE; JON A</creatorcontrib><creatorcontrib>FAROOQ; SHAJI</creatorcontrib><creatorcontrib>MULLER-LANDAU; FRIEDEL</creatorcontrib><creatorcontrib>GIESS; EDWARD A</creatorcontrib><creatorcontrib>DUNCOMBE; PETER R</creatorcontrib><creatorcontrib>VALLABHANENI; RAO</creatorcontrib><creatorcontrib>SHAW; ROBERT R</creatorcontrib><creatorcontrib>WALKER; GEORGE F</creatorcontrib><creatorcontrib>BROWNLOW, DECEASED; JAMES M</creatorcontrib><creatorcontrib>KIM; YOUNG-HO</creatorcontrib><creatorcontrib>AOUDE; FARID Y</creatorcontrib><creatorcontrib>NEISSER; MARK O</creatorcontrib><creatorcontrib>PARK; JAE M</creatorcontrib><creatorcontrib>KIM; JUNGIHL</creatorcontrib><creatorcontrib>RITA; ROBERT A</creatorcontrib><creatorcontrib>KNICKERBOCKER; SARAH H</creatorcontrib><creatorcontrib>SHAW; THOMAS M</creatorcontrib><creatorcontrib>COOPER; EMANUEL I</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>VAN HISE; JON A</au><au>FAROOQ; SHAJI</au><au>MULLER-LANDAU; FRIEDEL</au><au>GIESS; EDWARD A</au><au>DUNCOMBE; PETER R</au><au>VALLABHANENI; RAO</au><au>SHAW; ROBERT R</au><au>WALKER; GEORGE F</au><au>BROWNLOW, DECEASED; JAMES M</au><au>KIM; YOUNG-HO</au><au>AOUDE; FARID Y</au><au>NEISSER; MARK O</au><au>PARK; JAE M</au><au>KIM; JUNGIHL</au><au>RITA; ROBERT A</au><au>KNICKERBOCKER; SARAH H</au><au>SHAW; THOMAS M</au><au>COOPER; EMANUEL I</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Via paste compositions and use thereof to form conductive vias in circuitized ceramic substrates</title><date>1994-02-01</date><risdate>1994</risdate><abstract>Improved via-filling compositions for producing conductive vias in circuitized ceramic substrates, particularly multilayer substrates, without cracking and/or loss of hermetic sealing. The via-filling compositions comprise pastes containing a mixture of (a) ceramic and/or glass spheres of substantially- uniform diameter between about 0.5 and 6 (my)m, (b) conductive metal particles or spheres having a maximum dimension or diameter between about 1/3 and 1/4 of the diameter of the ceramic and/or glass spheres, and (c) a binder vehicle. The formed conductive via bodies comprise a uniform conductive skeletal network of sintered metal particles densely packed within a uniform matrix of the co-sintered ceramic and/or glass spheres, which matrix is hermetically fused and integrated with ceramic layers forming the wall of the via in the ceramic circuit substrate.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS CABLES CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS CONDUCTORS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS INSULATORS MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES SEMICONDUCTOR DEVICES TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS |
title | Via paste compositions and use thereof to form conductive vias in circuitized ceramic substrates |
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