RISC system capable of simultaneously executing data interlocked shift and arithmetic/logic instructions in one clock cycle by bypassing register

First and second instructions are simultaneously fetched from a memory (620) to be respectively decoded by first and second instruction decoders (644, 645). An instruction execution unit includes a register file (650), an arithmetic and logic unit (651), and a shifter (652). A first comparator (132) compares a destination field (112) of the first instruction with a first source field (123) of the second instruction. The shifter (652) produces an output in association with immediate data (114) of the first instruction, the output being ordinarily stored in a register file (650). However, when both inputs of the comparator (132) are identical to each other, the output from the shifter (652) is supplied to an input (656) of the arithmetic and logic unit (651) via a bypass signal transmission path.