Method and apparatus for testing semiconductor integrated circuit

An apparatus for testing a semiconductor integrated circuit by using probe lines and sense lines, has a selection device for applying a selective signal in sequence to one of the probe lines, and electronic switch devices incorporated in the integrated circuit so that the electronic switch devices a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: AZUMAI, HIDEO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator AZUMAI
HIDEO
description An apparatus for testing a semiconductor integrated circuit by using probe lines and sense lines, has a selection device for applying a selective signal in sequence to one of the probe lines, and electronic switch devices incorporated in the integrated circuit so that the electronic switch devices and intersections, where the probe lines and sense lines intersect each other, are in one-to-one correspondence and the electronic switch devices can feed signals to their corresponding sense lines in response to selective signals applied to the probe lines. Each electronic switch device is connected to test points in the integrated circuit and connected to its corresponding sense line. Many level quantization devices are provided for generating many-level quantized signal, corresponding to one of combinations of binary signals on the test points connected to the electronic switches of each electronic switch device, to its corresponding sense line, and two-level quantization devices convert the many-level quantized signal, generated on each sense line, to reproduced binary signals corresponding to the one of combinations of the binary signals on the test points.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US5198757A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US5198757A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US5198757A3</originalsourceid><addsrcrecordid>eNrjZHD0TS3JyE9RSMwD4oKCxKLEktJihbT8IoWS1OKSzLx0heLU3Mzk_LyU0uQSoGhmXklqOlBRaopCcmZRcmlmCQ8Da1piTnEqL5TmZpB3cw1x9tBNLciPTy0uSExOzUstiQ8NNjW0tDA3NXc0JqwCAIqGMck</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and apparatus for testing semiconductor integrated circuit</title><source>esp@cenet</source><creator>AZUMAI; HIDEO</creator><creatorcontrib>AZUMAI; HIDEO</creatorcontrib><description>An apparatus for testing a semiconductor integrated circuit by using probe lines and sense lines, has a selection device for applying a selective signal in sequence to one of the probe lines, and electronic switch devices incorporated in the integrated circuit so that the electronic switch devices and intersections, where the probe lines and sense lines intersect each other, are in one-to-one correspondence and the electronic switch devices can feed signals to their corresponding sense lines in response to selective signals applied to the probe lines. Each electronic switch device is connected to test points in the integrated circuit and connected to its corresponding sense line. Many level quantization devices are provided for generating many-level quantized signal, corresponding to one of combinations of binary signals on the test points connected to the electronic switches of each electronic switch device, to its corresponding sense line, and two-level quantization devices convert the many-level quantized signal, generated on each sense line, to reproduced binary signals corresponding to the one of combinations of the binary signals on the test points.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; SEMICONDUCTOR DEVICES ; TESTING</subject><creationdate>1993</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19930330&amp;DB=EPODOC&amp;CC=US&amp;NR=5198757A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19930330&amp;DB=EPODOC&amp;CC=US&amp;NR=5198757A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>AZUMAI; HIDEO</creatorcontrib><title>Method and apparatus for testing semiconductor integrated circuit</title><description>An apparatus for testing a semiconductor integrated circuit by using probe lines and sense lines, has a selection device for applying a selective signal in sequence to one of the probe lines, and electronic switch devices incorporated in the integrated circuit so that the electronic switch devices and intersections, where the probe lines and sense lines intersect each other, are in one-to-one correspondence and the electronic switch devices can feed signals to their corresponding sense lines in response to selective signals applied to the probe lines. Each electronic switch device is connected to test points in the integrated circuit and connected to its corresponding sense line. Many level quantization devices are provided for generating many-level quantized signal, corresponding to one of combinations of binary signals on the test points connected to the electronic switches of each electronic switch device, to its corresponding sense line, and two-level quantization devices convert the many-level quantized signal, generated on each sense line, to reproduced binary signals corresponding to the one of combinations of the binary signals on the test points.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1993</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHD0TS3JyE9RSMwD4oKCxKLEktJihbT8IoWS1OKSzLx0heLU3Mzk_LyU0uQSoGhmXklqOlBRaopCcmZRcmlmCQ8Da1piTnEqL5TmZpB3cw1x9tBNLciPTy0uSExOzUstiQ8NNjW0tDA3NXc0JqwCAIqGMck</recordid><startdate>19930330</startdate><enddate>19930330</enddate><creator>AZUMAI; HIDEO</creator><scope>EVB</scope></search><sort><creationdate>19930330</creationdate><title>Method and apparatus for testing semiconductor integrated circuit</title><author>AZUMAI; HIDEO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5198757A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1993</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>AZUMAI; HIDEO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>AZUMAI; HIDEO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for testing semiconductor integrated circuit</title><date>1993-03-30</date><risdate>1993</risdate><abstract>An apparatus for testing a semiconductor integrated circuit by using probe lines and sense lines, has a selection device for applying a selective signal in sequence to one of the probe lines, and electronic switch devices incorporated in the integrated circuit so that the electronic switch devices and intersections, where the probe lines and sense lines intersect each other, are in one-to-one correspondence and the electronic switch devices can feed signals to their corresponding sense lines in response to selective signals applied to the probe lines. Each electronic switch device is connected to test points in the integrated circuit and connected to its corresponding sense line. Many level quantization devices are provided for generating many-level quantized signal, corresponding to one of combinations of binary signals on the test points connected to the electronic switches of each electronic switch device, to its corresponding sense line, and two-level quantization devices convert the many-level quantized signal, generated on each sense line, to reproduced binary signals corresponding to the one of combinations of the binary signals on the test points.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US5198757A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
title Method and apparatus for testing semiconductor integrated circuit
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T10%3A04%3A06IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=AZUMAI;%20HIDEO&rft.date=1993-03-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS5198757A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true