Multiprocessor bus locking system with a winning processor broadcasting an ownership signal causing all processors to halt their requests

A method and apparatus for granting, to a select processor in a multiprocessor computing system, exclusive access to a bus for issuance of address, data and command signals thereover, wherein each processor includes bus lock request and bus lock assert elements which provide corresponding bus reques...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	MILIA, ANDREW, FLAHIVE, BARRY J, BAHR, RICHARD G
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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