Semiconductor memory device having means for repairing the memory device with respect to possible defective memory portions

A memory cell array (100) of an EPROM includes a first data memory region (1a), a second data memory region (1b), a 2M code memory line (2a) and a 1M code memory line (2b). When both the first and the second data memory regions (1a, 1b) are normal, the EPROM may be used as a 2M bit EPROM, in which c...

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Hauptverfasser:	MAKIHARA, HIROYASU, KOURO, YASUHIRO, KOHDA, KENJI, TOYAMA, TSUYOSHI
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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