Fabrication of GaAs integrated circuits

A process for manufacturing selectively doped heterostructure field-effect transistors (SDHTs), a desired wafer structure for SDHT fabrication and a method for isolating SDHTs on the wafer are disclosed herein. The wafer has epitaxial layers grown on a substrate. The layers are: a buffer layer of GaAs, a first spacer layer of AlGaAs, a donor layer of AlGaAs, a second spacer layer of AlGaAs, a first cap layer of GaAs, an etch-stop layer of AlGaAs and a second cap layer of GaAs. A protective layer of AlGaAs may then be grown on the second cap layer to protect the second cap layer from contamination or damage. Also a superlattice may first be grown on the substrate. Openings are made in the protective layer and then in the second cap layer where enhancement type SDHTs are to be formed. The remaining protective layer is then etched along with the exposed etch-stop layer with a selective etch to expose the first cap layer and the second cap layer where respective enhancement-type SDHTs and depletion-type SDHTs are to be formed. Gate electrodes for corresponding SDHTs are then formed on the exposed first and second cap layers and a subsequent selective dopant implant forms self-aligned SDHT structures. Multiple layers of dielectric and metal are then deposited to interconnect the SDHTs. The selective etch of the AlGaAs protective layer and the etch-stop layer results in consistent threshold voltages of the SDHTs across the wafer. The isolation of SDHTs is accomplished in a two step isolation involving implanting isolation dopant (e.g., oxygen) into the epitaxial layers.