Method for physical VLSI-chip design

For the physical design of a very large scale integration (VSLI) chip, a method is provided to implement a high density master image that contains logic and RAMs. In a hierarchical top-down design methodology, the circuitry to be contained on the chip is logically divided into partitions that are ma...

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Bibliographische Detailangaben

Hauptverfasser:	POLLMANN, KURT, ZUEHLKE, RAINER, SCHULZ, UWE, SCHETTLER, HELMUT, WAGNER, OTTO M, KLEIN, KLAUS
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES
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