Data communication arrangement with embedded matrix switch

Data communication arrangement with embedded matrix switch

Modems, data service units (109-111), application modules (108, 112, 114, 115) and other data communication devices (102-106), installed in a common equipment cabinet, are interconnected by way of a time division multiplexed bus (RB, WB, TSA, TYPE). Time slots assigned to the various devices recur a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: DOUSKALIS, WILLIAM
Format: Patent
Sprache:eng
Schlagworte:
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
MULTIPLEX COMMUNICATION
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator DOUSKALIS
WILLIAM
description Modems, data service units (109-111), application modules (108, 112, 114, 115) and other data communication devices (102-106), installed in a common equipment cabinet, are interconnected by way of a time division multiplexed bus (RB, WB, TSA, TYPE). Time slots assigned to the various devices recur at a number of regularly-spaced access periods across each time division multiplex frame. The rate at which the access periods occur and the total number of access periods that make up each frame are chosen in such a way as to accomodate a mix of devices having respective bus access rates wherein there is at least one pair of rates for which neither rate of the pair is a multiple of the other. The process of allocating access periods to the time slots is carried out using a known lemma to identify linear Diophantine equation solutions.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US4885741A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US4885741A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US4885741A3</originalsourceid><addsrcrecordid>eNrjZLBySSxJVEjOz80tzctMTizJzM9TSCwqSsxLT81NzStRKM8syVBIzU1KTUlJTVHITSwpyqxQKAaKJmfwMLCmJeYUp_JCaW4GeTfXEGcP3dSC_PjU4oLE5NS81JL40GATCwtTcxNDR2PCKgD2Ei7m</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Data communication arrangement with embedded matrix switch</title><source>esp@cenet</source><creator>DOUSKALIS; WILLIAM</creator><creatorcontrib>DOUSKALIS; WILLIAM</creatorcontrib><description>Modems, data service units (109-111), application modules (108, 112, 114, 115) and other data communication devices (102-106), installed in a common equipment cabinet, are interconnected by way of a time division multiplexed bus (RB, WB, TSA, TYPE). Time slots assigned to the various devices recur at a number of regularly-spaced access periods across each time division multiplex frame. The rate at which the access periods occur and the total number of access periods that make up each frame are chosen in such a way as to accomodate a mix of devices having respective bus access rates wherein there is at least one pair of rates for which neither rate of the pair is a multiple of the other. The process of allocating access periods to the time slots is carried out using a known lemma to identify linear Diophantine equation solutions.</description><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; MULTIPLEX COMMUNICATION ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>1989</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19891205&amp;DB=EPODOC&amp;CC=US&amp;NR=4885741A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19891205&amp;DB=EPODOC&amp;CC=US&amp;NR=4885741A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DOUSKALIS; WILLIAM</creatorcontrib><title>Data communication arrangement with embedded matrix switch</title><description>Modems, data service units (109-111), application modules (108, 112, 114, 115) and other data communication devices (102-106), installed in a common equipment cabinet, are interconnected by way of a time division multiplexed bus (RB, WB, TSA, TYPE). Time slots assigned to the various devices recur at a number of regularly-spaced access periods across each time division multiplex frame. The rate at which the access periods occur and the total number of access periods that make up each frame are chosen in such a way as to accomodate a mix of devices having respective bus access rates wherein there is at least one pair of rates for which neither rate of the pair is a multiple of the other. The process of allocating access periods to the time slots is carried out using a known lemma to identify linear Diophantine equation solutions.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>MULTIPLEX COMMUNICATION</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1989</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLBySSxJVEjOz80tzctMTizJzM9TSCwqSsxLT81NzStRKM8syVBIzU1KTUlJTVHITSwpyqxQKAaKJmfwMLCmJeYUp_JCaW4GeTfXEGcP3dSC_PjU4oLE5NS81JL40GATCwtTcxNDR2PCKgD2Ei7m</recordid><startdate>19891205</startdate><enddate>19891205</enddate><creator>DOUSKALIS; WILLIAM</creator><scope>EVB</scope></search><sort><creationdate>19891205</creationdate><title>Data communication arrangement with embedded matrix switch</title><author>DOUSKALIS; WILLIAM</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US4885741A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1989</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>MULTIPLEX COMMUNICATION</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>DOUSKALIS; WILLIAM</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DOUSKALIS; WILLIAM</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Data communication arrangement with embedded matrix switch</title><date>1989-12-05</date><risdate>1989</risdate><abstract>Modems, data service units (109-111), application modules (108, 112, 114, 115) and other data communication devices (102-106), installed in a common equipment cabinet, are interconnected by way of a time division multiplexed bus (RB, WB, TSA, TYPE). Time slots assigned to the various devices recur at a number of regularly-spaced access periods across each time division multiplex frame. The rate at which the access periods occur and the total number of access periods that make up each frame are chosen in such a way as to accomodate a mix of devices having respective bus access rates wherein there is at least one pair of rates for which neither rate of the pair is a multiple of the other. The process of allocating access periods to the time slots is carried out using a known lemma to identify linear Diophantine equation solutions.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US4885741A
source esp@cenet
subjects ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
MULTIPLEX COMMUNICATION
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title Data communication arrangement with embedded matrix switch
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-19T07%3A29%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=DOUSKALIS;%20WILLIAM&rft.date=1989-12-05&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS4885741A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true