Viad chip capacitor and method for making same

A two pole viad chip capacitor that is activatable from either of its sides having a plurality of ceramic layers in a stack, each and every layer having only two vias, a first via in a first region of each layer and a second via in a second region of each layer; a first conductor in each of the firs...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: ROBBINS, WILLIAM L
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator ROBBINS
WILLIAM L
description A two pole viad chip capacitor that is activatable from either of its sides having a plurality of ceramic layers in a stack, each and every layer having only two vias, a first via in a first region of each layer and a second via in a second region of each layer; a first conductor in each of the first vias; a second conductor in each of the second vias; a stack of first capacitor plates being on first alternate ceramic layers and each first plate being in electrical contact with a first conductor; and a stack of second capacitor plates, the second plates being on second alternate ceramic layers that are interdigitated with the first alternate ceramic layers and in electrical contact with a second conductor.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US4864465A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US4864465A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US4864465A3</originalsourceid><addsrcrecordid>eNrjZNALy0xMUUjOyCxQSE4sSEzOLMkvUkjMS1HITS3JyE9RSANycxOzM_PSFYoTc1N5GFjTEnOKU3mhNDeDvJtriLOHbmpBfnxqMdCA1LzUkvjQYBMLMxMTM1NHY8IqABmHKV8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Viad chip capacitor and method for making same</title><source>esp@cenet</source><creator>ROBBINS; WILLIAM L</creator><creatorcontrib>ROBBINS; WILLIAM L</creatorcontrib><description>A two pole viad chip capacitor that is activatable from either of its sides having a plurality of ceramic layers in a stack, each and every layer having only two vias, a first via in a first region of each layer and a second via in a second region of each layer; a first conductor in each of the first vias; a second conductor in each of the second vias; a stack of first capacitor plates being on first alternate ceramic layers and each first plate being in electrical contact with a first conductor; and a stack of second capacitor plates, the second plates being on second alternate ceramic layers that are interdigitated with the first alternate ceramic layers and in electrical contact with a second conductor.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CAPACITORS ; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES ORLIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE ; ELECTRICITY ; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC ; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS ; TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ; TECHNICAL SUBJECTS COVERED BY FORMER USPC ; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><creationdate>1989</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19890905&amp;DB=EPODOC&amp;CC=US&amp;NR=4864465A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19890905&amp;DB=EPODOC&amp;CC=US&amp;NR=4864465A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ROBBINS; WILLIAM L</creatorcontrib><title>Viad chip capacitor and method for making same</title><description>A two pole viad chip capacitor that is activatable from either of its sides having a plurality of ceramic layers in a stack, each and every layer having only two vias, a first via in a first region of each layer and a second via in a second region of each layer; a first conductor in each of the first vias; a second conductor in each of the second vias; a stack of first capacitor plates being on first alternate ceramic layers and each first plate being in electrical contact with a first conductor; and a stack of second capacitor plates, the second plates being on second alternate ceramic layers that are interdigitated with the first alternate ceramic layers and in electrical contact with a second conductor.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CAPACITORS</subject><subject>CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES ORLIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE</subject><subject>ELECTRICITY</subject><subject>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</subject><subject>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1989</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNALy0xMUUjOyCxQSE4sSEzOLMkvUkjMS1HITS3JyE9RSANycxOzM_PSFYoTc1N5GFjTEnOKU3mhNDeDvJtriLOHbmpBfnxqMdCA1LzUkvjQYBMLMxMTM1NHY8IqABmHKV8</recordid><startdate>19890905</startdate><enddate>19890905</enddate><creator>ROBBINS; WILLIAM L</creator><scope>EVB</scope></search><sort><creationdate>19890905</creationdate><title>Viad chip capacitor and method for making same</title><author>ROBBINS; WILLIAM L</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US4864465A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1989</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CAPACITORS</topic><topic>CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES ORLIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE</topic><topic>ELECTRICITY</topic><topic>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</topic><topic>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</topic><toplevel>online_resources</toplevel><creatorcontrib>ROBBINS; WILLIAM L</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ROBBINS; WILLIAM L</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Viad chip capacitor and method for making same</title><date>1989-09-05</date><risdate>1989</risdate><abstract>A two pole viad chip capacitor that is activatable from either of its sides having a plurality of ceramic layers in a stack, each and every layer having only two vias, a first via in a first region of each layer and a second via in a second region of each layer; a first conductor in each of the first vias; a second conductor in each of the second vias; a stack of first capacitor plates being on first alternate ceramic layers and each first plate being in electrical contact with a first conductor; and a stack of second capacitor plates, the second plates being on second alternate ceramic layers that are interdigitated with the first alternate ceramic layers and in electrical contact with a second conductor.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US4864465A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
CAPACITORS
CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES ORLIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
ELECTRICITY
GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS
TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
TECHNICAL SUBJECTS COVERED BY FORMER USPC
TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
title Viad chip capacitor and method for making same
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-16T15%3A01%3A05IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=ROBBINS;%20WILLIAM%20L&rft.date=1989-09-05&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS4864465A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true