Polyphase parity generator circuit

A polyphase parity generator circuit for generating parity of multiple bit data values on a data bus during one or more phases of a bus cycle. The circuit includes a prestage circuit having a plurality of parallel decode circuits couplable to respective pairs of input data lines. Each decode circuit...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	STAMBAUGH, MARK A, SACARISEN, STEPHEN P
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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