Apparatus and method for effecting dynamic address translation in a microprocessor implemented data processing system

The performance of a multi-microprocessor implemented data processing system that emulates a mainframe system is enhanced and optimized in view of space and power constraints for purposes of address translation by providing RAM-based storage means of predetermined depth and width to function as a page address table. The storage means depth is set to at least provide bit space to represent the total number of fixed size pages possible in a given virtual memory space. The width of the storage means is set to at least provide bit space to represent the largest page number that might be encountered in the available real memory and to accommodate a predetermined number of bits that flag information pertinent to translation and system performance. Circuit means, including microcode, is provided for initializing and updating the contents of the storage means as required. Further, when the translation capability is off, a real out-of-bounds flag bit in the storage means can be used to dynamically insure that a real out-of-bounds condition is not produced. The storage means is coupled to the microprocessor address bus from when it receives the page portion of a virtual address for which a real address is desired.