Logic circuit
A logic circuit includes a driver transistor and a load transistor formed by a junction type or Schottky barrier type field effect transistor, and an input terminal connected to a gate of the driving transistor. A gate voltage generator is connected to a gate of the load transistor and generates a l...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | SUYAMA KATSUHIKO |
description | A logic circuit includes a driver transistor and a load transistor formed by a junction type or Schottky barrier type field effect transistor, and an input terminal connected to a gate of the driving transistor. A gate voltage generator is connected to a gate of the load transistor and generates a level higher than the sum of threshold values of the load transistor and the driver transistor and lower than the lowest value of (1) the sum of a built-in voltage of the load transistor and the threshold voltage of the driver transistor and (2) the sum of a built-in voltage of the driver transistor and the threshold voltage of the load transistor. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US4656611A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US4656611A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US4656611A3</originalsourceid><addsrcrecordid>eNrjZOD1yU_PTFZIzixKLs0s4WFgTUvMKU7lhdLcDPJuriHOHrqpBfnxqcUFicmpeakl8aHBJmamZmaGho7GhFUAALtTHVk</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Logic circuit</title><source>esp@cenet</source><creator>SUYAMA; KATSUHIKO</creator><creatorcontrib>SUYAMA; KATSUHIKO</creatorcontrib><description>A logic circuit includes a driver transistor and a load transistor formed by a junction type or Schottky barrier type field effect transistor, and an input terminal connected to a gate of the driving transistor. A gate voltage generator is connected to a gate of the load transistor and generates a level higher than the sum of threshold values of the load transistor and the driver transistor and lower than the lowest value of (1) the sum of a built-in voltage of the load transistor and the threshold voltage of the driver transistor and (2) the sum of a built-in voltage of the driver transistor and the threshold voltage of the load transistor.</description><edition>4</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; BASIC ELECTRONIC CIRCUITRY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; PULSE TECHNIQUE ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>1987</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19870407&DB=EPODOC&CC=US&NR=4656611A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19870407&DB=EPODOC&CC=US&NR=4656611A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SUYAMA; KATSUHIKO</creatorcontrib><title>Logic circuit</title><description>A logic circuit includes a driver transistor and a load transistor formed by a junction type or Schottky barrier type field effect transistor, and an input terminal connected to a gate of the driving transistor. A gate voltage generator is connected to a gate of the load transistor and generates a level higher than the sum of threshold values of the load transistor and the driver transistor and lower than the lowest value of (1) the sum of a built-in voltage of the load transistor and the threshold voltage of the driver transistor and (2) the sum of a built-in voltage of the driver transistor and the threshold voltage of the load transistor.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1987</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOD1yU_PTFZIzixKLs0s4WFgTUvMKU7lhdLcDPJuriHOHrqpBfnxqcUFicmpeakl8aHBJmamZmaGho7GhFUAALtTHVk</recordid><startdate>19870407</startdate><enddate>19870407</enddate><creator>SUYAMA; KATSUHIKO</creator><scope>EVB</scope></search><sort><creationdate>19870407</creationdate><title>Logic circuit</title><author>SUYAMA; KATSUHIKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US4656611A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1987</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>SUYAMA; KATSUHIKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SUYAMA; KATSUHIKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Logic circuit</title><date>1987-04-07</date><risdate>1987</risdate><abstract>A logic circuit includes a driver transistor and a load transistor formed by a junction type or Schottky barrier type field effect transistor, and an input terminal connected to a gate of the driving transistor. A gate voltage generator is connected to a gate of the load transistor and generates a level higher than the sum of threshold values of the load transistor and the driver transistor and lower than the lowest value of (1) the sum of a built-in voltage of the load transistor and the threshold voltage of the driver transistor and (2) the sum of a built-in voltage of the driver transistor and the threshold voltage of the load transistor.</abstract><edition>4</edition><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US4656611A |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE SEMICONDUCTOR DEVICES STATIC STORES |
title | Logic circuit |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-14T23%3A55%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SUYAMA;%20KATSUHIKO&rft.date=1987-04-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS4656611A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |