High speed multiplier using carry-save/propagate pipeline with sparse carries
A high speed multiply apparatus minimizes latch requirements and I/O pin requirement between chips by a new configuration which iteratively adds four multiples of a multiplicand in a stage of 4-2 carry save adders which then feed four-bit parallel adders each having four sum outputs and a carry outp...
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| creator | LEVINE SAMUEL R WEINBERGER ARNOLD LETTENEY ROBERT C SHEN DAVID T |
| description | A high speed multiply apparatus minimizes latch requirements and I/O pin requirement between chips by a new configuration which iteratively adds four multiples of a multiplicand in a stage of 4-2 carry save adders which then feed four-bit parallel adders each having four sum outputs and a carry output from the highest order bit position. Only the sum outputs are latched and then fed to a carry propagate adder on each iteration for addition to the previous partial products. Only the single carry output from each of the 4-bit parallel adders needs to be latched and then fed to another 4-bit parallel adder. |
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| language | eng |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | High speed multiplier using carry-save/propagate pipeline with sparse carries |
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