Microprogrammable computer data transfer architecture

The invention relates to a microprogrammed computer whose architecture is determined by a simple and rigid format of the controlling micro-instruction. Each micro-instruction controls a data transfer and has at least four parts each of which are within a single micro-instruction. A first part always specifies the data source and data sink between which the data transfer is to take place. In a second part, conditions are stated for transfer to, or writing into the data sink. In a third part, a specific counting register out of a number of counting registers is addressed and, furthermore, it is specified how the contents of the counting register must be modified parallel to the transfer. In a fourth part, further data is contained; the fourth part may be controlled as a data source, with data transfer from the source to an arbitrary data sink being possible. In the case of transfer to the operation register of the arithmetic unit, such data indicates the logic or arithmetic operation. In the case of transfer to, for example, a counting register, the data may be employed to derive an initial address therefrom. The operation code register may advantageously have a capacity which corresponds to the length of two storage words.