Computer control apparatus

The first time period of the instruction fetch cycle is eliminated when fetching the branch to instruction in a computer system operating in a non-overlap mode. Whenever a branch instruction is decoded, the storage address register (SAR) is directly loaded during execution of the branch instruction...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	SMITH, RICHARD S, BODNER, RONALD E, SLACK, KEITH M, CROOKS, THOMAS L, MAGRISSO, ISRAEL B
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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