PRODUCTION OF SiO{11 {11 TAPERED FILMS

During SiO2 etching, when the oxide surface etch rate is larger than the bulk etch rate and the photoresist adheres tenaciously to the surface, a near vertical wall or cusp will be formed. This will create potential fracture spots in sputtered or evaporated metal which covers the steps. In the fabri...

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MOLINE R,US
description During SiO2 etching, when the oxide surface etch rate is larger than the bulk etch rate and the photoresist adheres tenaciously to the surface, a near vertical wall or cusp will be formed. This will create potential fracture spots in sputtered or evaporated metal which covers the steps. In the fabrication of self-aligned gate IGFETs, where the gate material acts as a mask against either etching or ion implantation, holes in the step metal will allow regions under the nominal gate to be doped during the source-drain doping.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US3769109A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US3769109A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US3769109A3</originalsourceid><addsrcrecordid>eNrjZFALCPJ3CXUO8fT3U_B3UwjO9K82NFQA4RDHANcgVxcFN08f32AeBta0xJziVF4ozc0g7-Ya4uyhm1qQH59aXJCYnJqXWhIfGmxsbmZpaGDpaExYBQBHryL-</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PRODUCTION OF SiO{11 {11 TAPERED FILMS</title><source>esp@cenet</source><creator>MAC RAE A,US ; MOLINE R,US</creator><creatorcontrib>MAC RAE A,US ; MOLINE R,US</creatorcontrib><description>During SiO2 etching, when the oxide surface etch rate is larger than the bulk etch rate and the photoresist adheres tenaciously to the surface, a near vertical wall or cusp will be formed. This will create potential fracture spots in sputtered or evaporated metal which covers the steps. In the fabrication of self-aligned gate IGFETs, where the gate material acts as a mask against either etching or ion implantation, holes in the step metal will allow regions under the nominal gate to be doped during the source-drain doping.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC ; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS ; SEMICONDUCTOR DEVICES ; TECHNICAL SUBJECTS COVERED BY FORMER USPC ; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS ; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS</subject><creationdate>1973</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19731030&amp;DB=EPODOC&amp;CC=US&amp;NR=3769109A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19731030&amp;DB=EPODOC&amp;CC=US&amp;NR=3769109A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MAC RAE A,US</creatorcontrib><creatorcontrib>MOLINE R,US</creatorcontrib><title>PRODUCTION OF SiO{11 {11 TAPERED FILMS</title><description>During SiO2 etching, when the oxide surface etch rate is larger than the bulk etch rate and the photoresist adheres tenaciously to the surface, a near vertical wall or cusp will be formed. This will create potential fracture spots in sputtered or evaporated metal which covers the steps. In the fabrication of self-aligned gate IGFETs, where the gate material acts as a mask against either etching or ion implantation, holes in the step metal will allow regions under the nominal gate to be doped during the source-drain doping.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</subject><subject>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1973</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFALCPJ3CXUO8fT3U_B3UwjO9K82NFQA4RDHANcgVxcFN08f32AeBta0xJziVF4ozc0g7-Ya4uyhm1qQH59aXJCYnJqXWhIfGmxsbmZpaGDpaExYBQBHryL-</recordid><startdate>19731030</startdate><enddate>19731030</enddate><creator>MAC RAE A,US</creator><creator>MOLINE R,US</creator><scope>EVB</scope></search><sort><creationdate>19731030</creationdate><title>PRODUCTION OF SiO{11 {11 TAPERED FILMS</title><author>MAC RAE A,US ; MOLINE R,US</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US3769109A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1973</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</topic><topic>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS</topic><toplevel>online_resources</toplevel><creatorcontrib>MAC RAE A,US</creatorcontrib><creatorcontrib>MOLINE R,US</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MAC RAE A,US</au><au>MOLINE R,US</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PRODUCTION OF SiO{11 {11 TAPERED FILMS</title><date>1973-10-30</date><risdate>1973</risdate><abstract>During SiO2 etching, when the oxide surface etch rate is larger than the bulk etch rate and the photoresist adheres tenaciously to the surface, a near vertical wall or cusp will be formed. This will create potential fracture spots in sputtered or evaporated metal which covers the steps. In the fabrication of self-aligned gate IGFETs, where the gate material acts as a mask against either etching or ion implantation, holes in the step metal will allow regions under the nominal gate to be doped during the source-drain doping.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS
SEMICONDUCTOR DEVICES
TECHNICAL SUBJECTS COVERED BY FORMER USPC
TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS
title PRODUCTION OF SiO{11 {11 TAPERED FILMS
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-15T03%3A42%3A13IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MAC%20RAE%20A,US&rft.date=1973-10-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS3769109A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true