VAPOR PHASE ETCHING AND POLISHING OF SEMICONDUCTORS
1,180,187. Etching. MOTOROLA Inc. 9 April, 1968 [8 May, 1967], No. 17008/68. Heading B6J. [Also in Divisions C7 and H1] Semi-conductor material, e.g. silicon or germanium, is etched or cleaned by contacting with a gaseous mixture of hydrogen and an interhalogen compound of fluorine while the tempera...
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| description | 1,180,187. Etching. MOTOROLA Inc. 9 April, 1968 [8 May, 1967], No. 17008/68. Heading B6J. [Also in Divisions C7 and H1] Semi-conductor material, e.g. silicon or germanium, is etched or cleaned by contacting with a gaseous mixture of hydrogen and an interhalogen compound of fluorine while the temperature of the semi-conductor material is maintained above 100 C. The interhalogen may be C1F, C1F 3 , BrF, BrF 3 , BrF 5 , IF 5 or IF 7 and the concentration of the interhalogen in a gas stream passing over the Si or Ge should be between 0À01% and 2% by weight, the nitrogen content being below 50 p.p.m. by weight. The apparatus used (Fig. 1, not shown) is similar to that disclosed in Specification 1,047,942. This etch-cleaning process may be an intermediate step in the formation of various semi-conductor devices, the methods of formation being analogous to those which are also disclosed in the above-mentioned Specification. The semi-conductor material is etched non-preferentially, that is, all the crystal structures present are attached to give a smooth surface. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US3511727A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US3511727A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US3511727A3</originalsourceid><addsrcrecordid>eNrjZDAOcwzwD1II8HAMdlVwDXH28PRzV3D0c1EI8PfxDAbz_N0Ugl19PZ39_VxCnUP8g4J5GFjTEnOKU3mhNDeDvBtIq25qQX58anFBYnJqXmpJfGiwsamhobmRuaMxYRUAC9kmeg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>VAPOR PHASE ETCHING AND POLISHING OF SEMICONDUCTORS</title><source>esp@cenet</source><creator>ROBERT G. HAYS</creator><creatorcontrib>ROBERT G. HAYS</creatorcontrib><description>1,180,187. Etching. MOTOROLA Inc. 9 April, 1968 [8 May, 1967], No. 17008/68. Heading B6J. [Also in Divisions C7 and H1] Semi-conductor material, e.g. silicon or germanium, is etched or cleaned by contacting with a gaseous mixture of hydrogen and an interhalogen compound of fluorine while the temperature of the semi-conductor material is maintained above 100 C. The interhalogen may be C1F, C1F 3 , BrF, BrF 3 , BrF 5 , IF 5 or IF 7 and the concentration of the interhalogen in a gas stream passing over the Si or Ge should be between 0À01% and 2% by weight, the nitrogen content being below 50 p.p.m. by weight. The apparatus used (Fig. 1, not shown) is similar to that disclosed in Specification 1,047,942. This etch-cleaning process may be an intermediate step in the formation of various semi-conductor devices, the methods of formation being analogous to those which are also disclosed in the above-mentioned Specification. The semi-conductor material is etched non-preferentially, that is, all the crystal structures present are attached to give a smooth surface.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CHEMICAL SURFACE TREATMENT ; CHEMISTRY ; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL ; COATING MATERIAL WITH METALLIC MATERIAL ; COATING METALLIC MATERIAL ; DIFFUSION TREATMENT OF METALLIC MATERIAL ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL ; METALLURGY ; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLICMATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASSC23 AND AT LEAST ONEPROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25 ; NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE ; SEMICONDUCTOR DEVICES</subject><creationdate>1970</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19700512&DB=EPODOC&CC=US&NR=3511727A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19700512&DB=EPODOC&CC=US&NR=3511727A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ROBERT G. HAYS</creatorcontrib><title>VAPOR PHASE ETCHING AND POLISHING OF SEMICONDUCTORS</title><description>1,180,187. Etching. MOTOROLA Inc. 9 April, 1968 [8 May, 1967], No. 17008/68. Heading B6J. [Also in Divisions C7 and H1] Semi-conductor material, e.g. silicon or germanium, is etched or cleaned by contacting with a gaseous mixture of hydrogen and an interhalogen compound of fluorine while the temperature of the semi-conductor material is maintained above 100 C. The interhalogen may be C1F, C1F 3 , BrF, BrF 3 , BrF 5 , IF 5 or IF 7 and the concentration of the interhalogen in a gas stream passing over the Si or Ge should be between 0À01% and 2% by weight, the nitrogen content being below 50 p.p.m. by weight. The apparatus used (Fig. 1, not shown) is similar to that disclosed in Specification 1,047,942. This etch-cleaning process may be an intermediate step in the formation of various semi-conductor devices, the methods of formation being analogous to those which are also disclosed in the above-mentioned Specification. The semi-conductor material is etched non-preferentially, that is, all the crystal structures present are attached to give a smooth surface.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CHEMICAL SURFACE TREATMENT</subject><subject>CHEMISTRY</subject><subject>COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL</subject><subject>COATING MATERIAL WITH METALLIC MATERIAL</subject><subject>COATING METALLIC MATERIAL</subject><subject>DIFFUSION TREATMENT OF METALLIC MATERIAL</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL</subject><subject>METALLURGY</subject><subject>MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLICMATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASSC23 AND AT LEAST ONEPROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25</subject><subject>NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1970</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAOcwzwD1II8HAMdlVwDXH28PRzV3D0c1EI8PfxDAbz_N0Ugl19PZ39_VxCnUP8g4J5GFjTEnOKU3mhNDeDvBtIq25qQX58anFBYnJqXmpJfGiwsamhobmRuaMxYRUAC9kmeg</recordid><startdate>19700512</startdate><enddate>19700512</enddate><creator>ROBERT G. HAYS</creator><scope>EVB</scope></search><sort><creationdate>19700512</creationdate><title>VAPOR PHASE ETCHING AND POLISHING OF SEMICONDUCTORS</title><author>ROBERT G. HAYS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US3511727A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1970</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CHEMICAL SURFACE TREATMENT</topic><topic>CHEMISTRY</topic><topic>COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL</topic><topic>COATING MATERIAL WITH METALLIC MATERIAL</topic><topic>COATING METALLIC MATERIAL</topic><topic>DIFFUSION TREATMENT OF METALLIC MATERIAL</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL</topic><topic>METALLURGY</topic><topic>MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLICMATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASSC23 AND AT LEAST ONEPROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25</topic><topic>NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>ROBERT G. HAYS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ROBERT G. HAYS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>VAPOR PHASE ETCHING AND POLISHING OF SEMICONDUCTORS</title><date>1970-05-12</date><risdate>1970</risdate><abstract>1,180,187. Etching. MOTOROLA Inc. 9 April, 1968 [8 May, 1967], No. 17008/68. Heading B6J. [Also in Divisions C7 and H1] Semi-conductor material, e.g. silicon or germanium, is etched or cleaned by contacting with a gaseous mixture of hydrogen and an interhalogen compound of fluorine while the temperature of the semi-conductor material is maintained above 100 C. The interhalogen may be C1F, C1F 3 , BrF, BrF 3 , BrF 5 , IF 5 or IF 7 and the concentration of the interhalogen in a gas stream passing over the Si or Ge should be between 0À01% and 2% by weight, the nitrogen content being below 50 p.p.m. by weight. The apparatus used (Fig. 1, not shown) is similar to that disclosed in Specification 1,047,942. This etch-cleaning process may be an intermediate step in the formation of various semi-conductor devices, the methods of formation being analogous to those which are also disclosed in the above-mentioned Specification. The semi-conductor material is etched non-preferentially, that is, all the crystal structures present are attached to give a smooth surface.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CHEMICAL SURFACE TREATMENT CHEMISTRY COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL COATING MATERIAL WITH METALLIC MATERIAL COATING METALLIC MATERIAL DIFFUSION TREATMENT OF METALLIC MATERIAL ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL METALLURGY MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLICMATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASSC23 AND AT LEAST ONEPROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25 NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE SEMICONDUCTOR DEVICES |
| title | VAPOR PHASE ETCHING AND POLISHING OF SEMICONDUCTORS |
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