Digital indicator circuitry
856,166. Circuits employing bi-stable magnetic elements. NATIONAL CASH REGISTER CO. Jan. 9, 1958 [Jan. 16, 1957], No. 864/58. Class 40 (9). [Also in Groups XIX and XXXV] A digital computer comprises a magnetic core data processing unit, and a programming unit for controlling the sequence of operatio...
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description | 856,166. Circuits employing bi-stable magnetic elements. NATIONAL CASH REGISTER CO. Jan. 9, 1958 [Jan. 16, 1957], No. 864/58. Class 40 (9). [Also in Groups XIX and XXXV] A digital computer comprises a magnetic core data processing unit, and a programming unit for controlling the sequence of operations performed in the processing unit, the programming unit being itself controlled by signals derived from the processing unit. General.-The computer described is applied to the positioning of a shaft 21, Fig. 1, of a device 17 indicating a vehicle bearing, a pulse on output line 68 or 69 moving the shaft and indicator pointer one step clockwise and counterclockwise, respectively. The shaft may be mechanically coupled to a synchro-receiver 26 controlling the vehicle steering mechanism. The programming unit 10 (Fig. 6) and data processing unit 12 (Fig. 5) each comprise similar magnetic core registers. The E register, Figs. 1, 3 and 5, receives serially from a matrix memory 11 an 8-digit binary number word representing a desired vehicle bearing, which is compared, at 23, Fig. 1, with the number in the F register representing the present bearing, the comparison result being given by the one-digit A register. If the numbers are unequal, the F-number is adjusted by adding or subtracting " 1's," corresponding pulses being supplied to line 69 or 68. This operation is performed by repetitive cycles of programme-unit-controlled operations (see Group XIX), each lasting for a word period, the " programme count " being given by the combination of binary outputs from registers J, K, L, Fig. 6. Timing pulses.-Generators 38, 40 and 39, Figs. 3 and 5, driven from pulse source 15, e.g. a multivibrator, produce half-drive pulses Cc, Cs and P 1 -P 8 , Fig. 3b, a pair of which of like polarity will drive a core to saturation in one direction or the other. As shown, a core switching cycle comprises 4 periods Rs, Wc, Rc, Ws. Pulses Cc, applied to register control cores, are effected during Wc, Rc for writing into and reading from such cores respectively; pulses Cs, applied to register storage cores, are similarly effective during Rs, Ws; and the digit-select pulses P 1 -P 8 are effective successively each during all 4 periods of a corresponding cycle. Pulses produced by a further generator 16, effective during write periods Wc, Ws, are combined in OR gate 20 and applied to register transfer circuits TC. Magnetic core registers; transfer circuits.- Each of the registers comprises one o |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US3017102A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US3017102A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US3017102A3</originalsourceid><addsrcrecordid>eNrjZJB2yUzPLEnMUcjMS8lMTizJL1JIzixKLs0sKarkYWBNS8wpTuWF0twM8m6uIc4euqkF-fGpxQWJyal5qSXxocHGBobmhgZGjsaEVQAABBIi4Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Digital indicator circuitry</title><source>esp@cenet</source><creator>ANDREWS LADIMER J</creator><creatorcontrib>ANDREWS LADIMER J</creatorcontrib><description>856,166. Circuits employing bi-stable magnetic elements. NATIONAL CASH REGISTER CO. Jan. 9, 1958 [Jan. 16, 1957], No. 864/58. Class 40 (9). [Also in Groups XIX and XXXV] A digital computer comprises a magnetic core data processing unit, and a programming unit for controlling the sequence of operations performed in the processing unit, the programming unit being itself controlled by signals derived from the processing unit. General.-The computer described is applied to the positioning of a shaft 21, Fig. 1, of a device 17 indicating a vehicle bearing, a pulse on output line 68 or 69 moving the shaft and indicator pointer one step clockwise and counterclockwise, respectively. The shaft may be mechanically coupled to a synchro-receiver 26 controlling the vehicle steering mechanism. The programming unit 10 (Fig. 6) and data processing unit 12 (Fig. 5) each comprise similar magnetic core registers. The E register, Figs. 1, 3 and 5, receives serially from a matrix memory 11 an 8-digit binary number word representing a desired vehicle bearing, which is compared, at 23, Fig. 1, with the number in the F register representing the present bearing, the comparison result being given by the one-digit A register. If the numbers are unequal, the F-number is adjusted by adding or subtracting " 1's," corresponding pulses being supplied to line 69 or 68. This operation is performed by repetitive cycles of programme-unit-controlled operations (see Group XIX), each lasting for a word period, the " programme count " being given by the combination of binary outputs from registers J, K, L, Fig. 6. Timing pulses.-Generators 38, 40 and 39, Figs. 3 and 5, driven from pulse source 15, e.g. a multivibrator, produce half-drive pulses Cc, Cs and P 1 -P 8 , Fig. 3b, a pair of which of like polarity will drive a core to saturation in one direction or the other. As shown, a core switching cycle comprises 4 periods Rs, Wc, Rc, Ws. Pulses Cc, applied to register control cores, are effected during Wc, Rc for writing into and reading from such cores respectively; pulses Cs, applied to register storage cores, are similarly effective during Rs, Ws; and the digit-select pulses P 1 -P 8 are effective successively each during all 4 periods of a corresponding cycle. Pulses produced by a further generator 16, effective during write periods Wc, Ws, are combined in OR gate 20 and applied to register transfer circuits TC. Magnetic core registers; transfer circuits.- Each of the registers comprises one or more storage cores, such as Els-E8s, Fig. 3, control cores such as Elc-E4c, and a transfer circuit TC. Each transfer circuit (Fig. 4, not shown), comprises a bistable flip-flop with input and output amplifier gates, and is controlled by a common core read-out wire such as 47 so as to provide a pulse on either its true or its false output, such as Es or Es1, during each write period. Selected transfer circuit outputs are applied to inhibit windings on the cores (as shown); and a core is driven from the " 0 " or false state to the " 1 " or true state, during a write period, only if none of the inhibit windings thereon receives a pulse. The switching is effected by pulses Cc, Cs, either alone, in which case the supply lines are doubly wound on the cores (as for Elc-E4c), or in combination with one of pulses P 1 -P 8 (as for Els-E8s). During the 4-period switching cycle, a register operates as follows: period Rs-pulse Cs, Fig. 3b, drives storage cores to " 0," and for any core previously in the " 1 " state an output pulse is produced on the read-out wire and applied to the associated transfer circuit; period Wc-pulse Cc causes that control core, if any, which is not inhibited by the transfer circuit outputs, to be driven to " 1 " ; period Rc-pulse Cc drives the control core to " 0," thus producing a transfercircuit-controlling read-out pulse if any control core was driven to " 1 " ; and period Ws-pulse Cs causes any uninhibited storage core to be driven to " I." For example, in the E register during period PC1, the programme-unit transfer circuit outputs Js1, Ks1, Ks, Ls1, Ls applied to the control cores, permit only E1c or E2c to be operative. If the false output Bs1 of a transfer circuit associated with memory 11, Fig. 1, is operative, core E2c is uninhibited provided E1s is inoperative, thus any " 1's " read from the storage cores E1s-E8s successively selected by pulses P 1 -P 8 , will be re-written in the same cores, while an " 0 " will cause E2c to be inhibited so that nothing is re-written. To enter a new number serially from memory 11 into the E register, if the true output Bs is rendered operative, core E1c is uninhibited for every " 1 " (output Ms1 not operative) in a new number from memory 11, whereby the cores E1s-E8s are set under control of P 1 -P 8 to staticize this number in place of the previous registration. In the programme unit, the J, K and L registers, Fig. 6, are unchanged during digit periods P 1 -P 7 but register a new programme count during P 8 under control of the transfer circuit outputs for all the registers, Figs. 5 and 6.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; CODE CONVERSION IN GENERAL ; CODING ; COMPUTING ; CONTROLLING ; COUNTING ; DECODING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; PULSE TECHNIQUE ; REGULATING ; STATIC STORES ; SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES</subject><creationdate>1962</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19620116&DB=EPODOC&CC=US&NR=3017102A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76294</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19620116&DB=EPODOC&CC=US&NR=3017102A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ANDREWS LADIMER J</creatorcontrib><title>Digital indicator circuitry</title><description>856,166. Circuits employing bi-stable magnetic elements. NATIONAL CASH REGISTER CO. Jan. 9, 1958 [Jan. 16, 1957], No. 864/58. Class 40 (9). [Also in Groups XIX and XXXV] A digital computer comprises a magnetic core data processing unit, and a programming unit for controlling the sequence of operations performed in the processing unit, the programming unit being itself controlled by signals derived from the processing unit. General.-The computer described is applied to the positioning of a shaft 21, Fig. 1, of a device 17 indicating a vehicle bearing, a pulse on output line 68 or 69 moving the shaft and indicator pointer one step clockwise and counterclockwise, respectively. The shaft may be mechanically coupled to a synchro-receiver 26 controlling the vehicle steering mechanism. The programming unit 10 (Fig. 6) and data processing unit 12 (Fig. 5) each comprise similar magnetic core registers. The E register, Figs. 1, 3 and 5, receives serially from a matrix memory 11 an 8-digit binary number word representing a desired vehicle bearing, which is compared, at 23, Fig. 1, with the number in the F register representing the present bearing, the comparison result being given by the one-digit A register. If the numbers are unequal, the F-number is adjusted by adding or subtracting " 1's," corresponding pulses being supplied to line 69 or 68. This operation is performed by repetitive cycles of programme-unit-controlled operations (see Group XIX), each lasting for a word period, the " programme count " being given by the combination of binary outputs from registers J, K, L, Fig. 6. Timing pulses.-Generators 38, 40 and 39, Figs. 3 and 5, driven from pulse source 15, e.g. a multivibrator, produce half-drive pulses Cc, Cs and P 1 -P 8 , Fig. 3b, a pair of which of like polarity will drive a core to saturation in one direction or the other. As shown, a core switching cycle comprises 4 periods Rs, Wc, Rc, Ws. Pulses Cc, applied to register control cores, are effected during Wc, Rc for writing into and reading from such cores respectively; pulses Cs, applied to register storage cores, are similarly effective during Rs, Ws; and the digit-select pulses P 1 -P 8 are effective successively each during all 4 periods of a corresponding cycle. Pulses produced by a further generator 16, effective during write periods Wc, Ws, are combined in OR gate 20 and applied to register transfer circuits TC. Magnetic core registers; transfer circuits.- Each of the registers comprises one or more storage cores, such as Els-E8s, Fig. 3, control cores such as Elc-E4c, and a transfer circuit TC. Each transfer circuit (Fig. 4, not shown), comprises a bistable flip-flop with input and output amplifier gates, and is controlled by a common core read-out wire such as 47 so as to provide a pulse on either its true or its false output, such as Es or Es1, during each write period. Selected transfer circuit outputs are applied to inhibit windings on the cores (as shown); and a core is driven from the " 0 " or false state to the " 1 " or true state, during a write period, only if none of the inhibit windings thereon receives a pulse. The switching is effected by pulses Cc, Cs, either alone, in which case the supply lines are doubly wound on the cores (as for Elc-E4c), or in combination with one of pulses P 1 -P 8 (as for Els-E8s). During the 4-period switching cycle, a register operates as follows: period Rs-pulse Cs, Fig. 3b, drives storage cores to " 0," and for any core previously in the " 1 " state an output pulse is produced on the read-out wire and applied to the associated transfer circuit; period Wc-pulse Cc causes that control core, if any, which is not inhibited by the transfer circuit outputs, to be driven to " 1 " ; period Rc-pulse Cc drives the control core to " 0," thus producing a transfercircuit-controlling read-out pulse if any control core was driven to " 1 " ; and period Ws-pulse Cs causes any uninhibited storage core to be driven to " I." For example, in the E register during period PC1, the programme-unit transfer circuit outputs Js1, Ks1, Ks, Ls1, Ls applied to the control cores, permit only E1c or E2c to be operative. If the false output Bs1 of a transfer circuit associated with memory 11, Fig. 1, is operative, core E2c is uninhibited provided E1s is inoperative, thus any " 1's " read from the storage cores E1s-E8s successively selected by pulses P 1 -P 8 , will be re-written in the same cores, while an " 0 " will cause E2c to be inhibited so that nothing is re-written. To enter a new number serially from memory 11 into the E register, if the true output Bs is rendered operative, core E1c is uninhibited for every " 1 " (output Ms1 not operative) in a new number from memory 11, whereby the cores E1s-E8s are set under control of P 1 -P 8 to staticize this number in place of the previous registration. In the programme unit, the J, K and L registers, Fig. 6, are unchanged during digit periods P 1 -P 7 but register a new programme count during P 8 under control of the transfer circuit outputs for all the registers, Figs. 5 and 6.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>CODE CONVERSION IN GENERAL</subject><subject>CODING</subject><subject>COMPUTING</subject><subject>CONTROLLING</subject><subject>COUNTING</subject><subject>DECODING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>REGULATING</subject><subject>STATIC STORES</subject><subject>SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1962</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJB2yUzPLEnMUcjMS8lMTizJL1JIzixKLs0sKarkYWBNS8wpTuWF0twM8m6uIc4euqkF-fGpxQWJyal5qSXxocHGBobmhgZGjsaEVQAABBIi4Q</recordid><startdate>19620116</startdate><enddate>19620116</enddate><creator>ANDREWS LADIMER J</creator><scope>EVB</scope></search><sort><creationdate>19620116</creationdate><title>Digital indicator circuitry</title><author>ANDREWS LADIMER J</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US3017102A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1962</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>CODE CONVERSION IN GENERAL</topic><topic>CODING</topic><topic>COMPUTING</topic><topic>CONTROLLING</topic><topic>COUNTING</topic><topic>DECODING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>REGULATING</topic><topic>STATIC STORES</topic><topic>SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES</topic><toplevel>online_resources</toplevel><creatorcontrib>ANDREWS LADIMER J</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ANDREWS LADIMER J</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Digital indicator circuitry</title><date>1962-01-16</date><risdate>1962</risdate><abstract>856,166. Circuits employing bi-stable magnetic elements. NATIONAL CASH REGISTER CO. Jan. 9, 1958 [Jan. 16, 1957], No. 864/58. Class 40 (9). [Also in Groups XIX and XXXV] A digital computer comprises a magnetic core data processing unit, and a programming unit for controlling the sequence of operations performed in the processing unit, the programming unit being itself controlled by signals derived from the processing unit. General.-The computer described is applied to the positioning of a shaft 21, Fig. 1, of a device 17 indicating a vehicle bearing, a pulse on output line 68 or 69 moving the shaft and indicator pointer one step clockwise and counterclockwise, respectively. The shaft may be mechanically coupled to a synchro-receiver 26 controlling the vehicle steering mechanism. The programming unit 10 (Fig. 6) and data processing unit 12 (Fig. 5) each comprise similar magnetic core registers. The E register, Figs. 1, 3 and 5, receives serially from a matrix memory 11 an 8-digit binary number word representing a desired vehicle bearing, which is compared, at 23, Fig. 1, with the number in the F register representing the present bearing, the comparison result being given by the one-digit A register. If the numbers are unequal, the F-number is adjusted by adding or subtracting " 1's," corresponding pulses being supplied to line 69 or 68. This operation is performed by repetitive cycles of programme-unit-controlled operations (see Group XIX), each lasting for a word period, the " programme count " being given by the combination of binary outputs from registers J, K, L, Fig. 6. Timing pulses.-Generators 38, 40 and 39, Figs. 3 and 5, driven from pulse source 15, e.g. a multivibrator, produce half-drive pulses Cc, Cs and P 1 -P 8 , Fig. 3b, a pair of which of like polarity will drive a core to saturation in one direction or the other. As shown, a core switching cycle comprises 4 periods Rs, Wc, Rc, Ws. Pulses Cc, applied to register control cores, are effected during Wc, Rc for writing into and reading from such cores respectively; pulses Cs, applied to register storage cores, are similarly effective during Rs, Ws; and the digit-select pulses P 1 -P 8 are effective successively each during all 4 periods of a corresponding cycle. Pulses produced by a further generator 16, effective during write periods Wc, Ws, are combined in OR gate 20 and applied to register transfer circuits TC. Magnetic core registers; transfer circuits.- Each of the registers comprises one or more storage cores, such as Els-E8s, Fig. 3, control cores such as Elc-E4c, and a transfer circuit TC. Each transfer circuit (Fig. 4, not shown), comprises a bistable flip-flop with input and output amplifier gates, and is controlled by a common core read-out wire such as 47 so as to provide a pulse on either its true or its false output, such as Es or Es1, during each write period. Selected transfer circuit outputs are applied to inhibit windings on the cores (as shown); and a core is driven from the " 0 " or false state to the " 1 " or true state, during a write period, only if none of the inhibit windings thereon receives a pulse. The switching is effected by pulses Cc, Cs, either alone, in which case the supply lines are doubly wound on the cores (as for Elc-E4c), or in combination with one of pulses P 1 -P 8 (as for Els-E8s). During the 4-period switching cycle, a register operates as follows: period Rs-pulse Cs, Fig. 3b, drives storage cores to " 0," and for any core previously in the " 1 " state an output pulse is produced on the read-out wire and applied to the associated transfer circuit; period Wc-pulse Cc causes that control core, if any, which is not inhibited by the transfer circuit outputs, to be driven to " 1 " ; period Rc-pulse Cc drives the control core to " 0," thus producing a transfercircuit-controlling read-out pulse if any control core was driven to " 1 " ; and period Ws-pulse Cs causes any uninhibited storage core to be driven to " I." For example, in the E register during period PC1, the programme-unit transfer circuit outputs Js1, Ks1, Ks, Ls1, Ls applied to the control cores, permit only E1c or E2c to be operative. If the false output Bs1 of a transfer circuit associated with memory 11, Fig. 1, is operative, core E2c is uninhibited provided E1s is inoperative, thus any " 1's " read from the storage cores E1s-E8s successively selected by pulses P 1 -P 8 , will be re-written in the same cores, while an " 0 " will cause E2c to be inhibited so that nothing is re-written. To enter a new number serially from memory 11 into the E register, if the true output Bs is rendered operative, core E1c is uninhibited for every " 1 " (output Ms1 not operative) in a new number from memory 11, whereby the cores E1s-E8s are set under control of P 1 -P 8 to staticize this number in place of the previous registration. In the programme unit, the J, K and L registers, Fig. 6, are unchanged during digit periods P 1 -P 7 but register a new programme count during P 8 under control of the transfer circuit outputs for all the registers, Figs. 5 and 6.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRONIC CIRCUITRY CALCULATING CODE CONVERSION IN GENERAL CODING COMPUTING CONTROLLING COUNTING DECODING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE REGULATING STATIC STORES SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES |
title | Digital indicator circuitry |
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