SEMICONDUCTOR DEVICE ARRANGEMENT AND METHOD OF MANUFACTURING THE SAME
An embodiment of the present disclosure provides a semiconductor device arrangement. This semiconductor device arrangement includes a carrier, a first semiconductor device, a second semiconductor device, a first adhesive portion, and a second adhesive portion. The first semiconductor device and the...
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| creator | HU, Wei-Shan CHEN, Chien-Chih CHENG, Ching-Tai |
| description | An embodiment of the present disclosure provides a semiconductor device arrangement. This semiconductor device arrangement includes a carrier, a first semiconductor device, a second semiconductor device, a first adhesive portion, and a second adhesive portion. The first semiconductor device and the second semiconductor device are separately arranged on the carrier. The first adhesive portion and the second adhesive portion are separately arranged on the carrier, the first adhesive portion is located between the first semiconductor device and the carrier, and the second adhesive portion is located between the second semiconductor device and the carrier. In the cross-sectional view, the first adhesive portion includes an inclined sidewall, and the inclined sidewall is adjacent to the carrier and forms an interior angle greater than 90 degrees to the carrier. |
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This semiconductor device arrangement includes a carrier, a first semiconductor device, a second semiconductor device, a first adhesive portion, and a second adhesive portion. The first semiconductor device and the second semiconductor device are separately arranged on the carrier. The first adhesive portion and the second adhesive portion are separately arranged on the carrier, the first adhesive portion is located between the first semiconductor device and the carrier, and the second adhesive portion is located between the second semiconductor device and the carrier. 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In the cross-sectional view, the first adhesive portion includes an inclined sidewall, and the inclined sidewall is adjacent to the carrier and forms an interior angle greater than 90 degrees to the carrier.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>LAYERED PRODUCTS</subject><subject>LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM</subject><subject>PERFORMING OPERATIONS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TRANSPORTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAQANAsDqL-w4GzUGOHOh7JpcmQCyQX11IkTqKF-v-4-AFOb3lbRYViMIltNZIyWLoFQ4A5I48UiQWQLUQSnywkBxG5OjRSc-ARxBMUjLRXm8f8XNvh504dHYnxp7a8p7Yu87292meqRXe673V3HQY8X_5bXzPnLPU</recordid><startdate>20241219</startdate><enddate>20241219</enddate><creator>HU, Wei-Shan</creator><creator>CHEN, Chien-Chih</creator><creator>CHENG, Ching-Tai</creator><scope>EVB</scope></search><sort><creationdate>20241219</creationdate><title>SEMICONDUCTOR DEVICE ARRANGEMENT AND METHOD OF MANUFACTURING THE SAME</title><author>HU, Wei-Shan ; CHEN, Chien-Chih ; CHENG, Ching-Tai</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024420988A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>LAYERED PRODUCTS</topic><topic>LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM</topic><topic>PERFORMING OPERATIONS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TRANSPORTING</topic><toplevel>online_resources</toplevel><creatorcontrib>HU, Wei-Shan</creatorcontrib><creatorcontrib>CHEN, Chien-Chih</creatorcontrib><creatorcontrib>CHENG, Ching-Tai</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HU, Wei-Shan</au><au>CHEN, Chien-Chih</au><au>CHENG, Ching-Tai</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE ARRANGEMENT AND METHOD OF MANUFACTURING THE SAME</title><date>2024-12-19</date><risdate>2024</risdate><abstract>An embodiment of the present disclosure provides a semiconductor device arrangement. This semiconductor device arrangement includes a carrier, a first semiconductor device, a second semiconductor device, a first adhesive portion, and a second adhesive portion. The first semiconductor device and the second semiconductor device are separately arranged on the carrier. The first adhesive portion and the second adhesive portion are separately arranged on the carrier, the first adhesive portion is located between the first semiconductor device and the carrier, and the second adhesive portion is located between the second semiconductor device and the carrier. In the cross-sectional view, the first adhesive portion includes an inclined sidewall, and the inclined sidewall is adjacent to the carrier and forms an interior angle greater than 90 degrees to the carrier.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY LAYERED PRODUCTS LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM PERFORMING OPERATIONS SEMICONDUCTOR DEVICES TRANSPORTING |
| title | SEMICONDUCTOR DEVICE ARRANGEMENT AND METHOD OF MANUFACTURING THE SAME |
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