ACCELERATING LOW-DENSITY PARITY-CHECK DECODING VIA SCHEDULING, AND RELATED DEVICES, METHODS AND COMPUTER PROGRAMS

ACCELERATING LOW-DENSITY PARITY-CHECK DECODING VIA SCHEDULING, AND RELATED DEVICES, METHODS AND COMPUTER PROGRAMS

Devices, methods and computer programs for accelerating low-density parity-check (LDPC) decoding via scheduling are disclosed. At least some of the example embodiments described herein may allow reducing cost and improving power efficiency beyond that of semiconductor processor scaling currently use...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: LING, Jonathan, Cautereels, Paul
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRICITY
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator LING, Jonathan
Cautereels, Paul
description Devices, methods and computer programs for accelerating low-density parity-check (LDPC) decoding via scheduling are disclosed. At least some of the example embodiments described herein may allow reducing cost and improving power efficiency beyond that of semiconductor processor scaling currently used in accelerating LDPC decoding.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024405784A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024405784A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024405784A13</originalsourceid><addsrcrecordid>eNqNikEKwjAQRbtxIeodBty2ULWi22EytsG0KUlacVWKxJVopd4fo3gAV4__35tGTyRixQadrHJQ-pQIrqx0Z6jRBCRUMB1BMGnxKVqJYMMnGhVmDFgJMKzQsQhRK4ltDCW7Qgv7laTLunFsoDY6N1jaeTS59rfRL36cRcsDOyoSPzw6Pw79xd_9q2vsOl1nWbrd7TNcbf6r3shqOMw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ACCELERATING LOW-DENSITY PARITY-CHECK DECODING VIA SCHEDULING, AND RELATED DEVICES, METHODS AND COMPUTER PROGRAMS</title><source>esp@cenet</source><creator>LING, Jonathan ; Cautereels, Paul</creator><creatorcontrib>LING, Jonathan ; Cautereels, Paul</creatorcontrib><description>Devices, methods and computer programs for accelerating low-density parity-check (LDPC) decoding via scheduling are disclosed. At least some of the example embodiments described herein may allow reducing cost and improving power efficiency beyond that of semiconductor processor scaling currently used in accelerating LDPC decoding.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CODE CONVERSION IN GENERAL ; CODING ; DECODING ; ELECTRICITY</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241205&amp;DB=EPODOC&amp;CC=US&amp;NR=2024405784A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241205&amp;DB=EPODOC&amp;CC=US&amp;NR=2024405784A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LING, Jonathan</creatorcontrib><creatorcontrib>Cautereels, Paul</creatorcontrib><title>ACCELERATING LOW-DENSITY PARITY-CHECK DECODING VIA SCHEDULING, AND RELATED DEVICES, METHODS AND COMPUTER PROGRAMS</title><description>Devices, methods and computer programs for accelerating low-density parity-check (LDPC) decoding via scheduling are disclosed. At least some of the example embodiments described herein may allow reducing cost and improving power efficiency beyond that of semiconductor processor scaling currently used in accelerating LDPC decoding.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CODE CONVERSION IN GENERAL</subject><subject>CODING</subject><subject>DECODING</subject><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNikEKwjAQRbtxIeodBty2ULWi22EytsG0KUlacVWKxJVopd4fo3gAV4__35tGTyRixQadrHJQ-pQIrqx0Z6jRBCRUMB1BMGnxKVqJYMMnGhVmDFgJMKzQsQhRK4ltDCW7Qgv7laTLunFsoDY6N1jaeTS59rfRL36cRcsDOyoSPzw6Pw79xd_9q2vsOl1nWbrd7TNcbf6r3shqOMw</recordid><startdate>20241205</startdate><enddate>20241205</enddate><creator>LING, Jonathan</creator><creator>Cautereels, Paul</creator><scope>EVB</scope></search><sort><creationdate>20241205</creationdate><title>ACCELERATING LOW-DENSITY PARITY-CHECK DECODING VIA SCHEDULING, AND RELATED DEVICES, METHODS AND COMPUTER PROGRAMS</title><author>LING, Jonathan ; Cautereels, Paul</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024405784A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CODE CONVERSION IN GENERAL</topic><topic>CODING</topic><topic>DECODING</topic><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>LING, Jonathan</creatorcontrib><creatorcontrib>Cautereels, Paul</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LING, Jonathan</au><au>Cautereels, Paul</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ACCELERATING LOW-DENSITY PARITY-CHECK DECODING VIA SCHEDULING, AND RELATED DEVICES, METHODS AND COMPUTER PROGRAMS</title><date>2024-12-05</date><risdate>2024</risdate><abstract>Devices, methods and computer programs for accelerating low-density parity-check (LDPC) decoding via scheduling are disclosed. At least some of the example embodiments described herein may allow reducing cost and improving power efficiency beyond that of semiconductor processor scaling currently used in accelerating LDPC decoding.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2024405784A1
source esp@cenet
subjects BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRICITY
title ACCELERATING LOW-DENSITY PARITY-CHECK DECODING VIA SCHEDULING, AND RELATED DEVICES, METHODS AND COMPUTER PROGRAMS
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-16T18%3A42%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LING,%20Jonathan&rft.date=2024-12-05&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024405784A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true