GATE DRIVING CIRCUIT AND DISPLAY DEVICE INCLUDING GATE DRIVING CIRCUIT

The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit, and more particularly, to a gate driving circuit having a reduced size and a display device including the gate driving circuit. The gate driving circuit comprises a plurality of dummy st...

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Hauptverfasser: CHOI, Jaeyi, YUN, Seongho, CHOI, SooHong
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creator CHOI, Jaeyi
YUN, Seongho
CHOI, SooHong
description The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit, and more particularly, to a gate driving circuit having a reduced size and a display device including the gate driving circuit. The gate driving circuit comprises a plurality of dummy stage circuits and stage circuits, which supply gate signals to each gate line and comprise a Q node, a QH node, and a QB node. A gate signal output circuit included in each of the stage circuits can output first to j-th gate signals based on first to j-th scan clock signals or a first low voltage according to the voltage level of the Q node or the voltage level of the QB node.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024395216A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024395216A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024395216A13</originalsourceid><addsrcrecordid>eNrjZHBzdwxxVXAJ8gzz9HNXcPYMcg71DFFw9HNRcPEMDvBxjFRwcQ3zdHZV8PRz9gl1ASnCpoOHgTUtMac4lRdKczMou7mGOHvophbkx6cWFyQmp-allsSHBhsZGJkYW5oaGZo5GhoTpwoAQG4tCQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>GATE DRIVING CIRCUIT AND DISPLAY DEVICE INCLUDING GATE DRIVING CIRCUIT</title><source>esp@cenet</source><creator>CHOI, Jaeyi ; YUN, Seongho ; CHOI, SooHong</creator><creatorcontrib>CHOI, Jaeyi ; YUN, Seongho ; CHOI, SooHong</creatorcontrib><description>The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit, and more particularly, to a gate driving circuit having a reduced size and a display device including the gate driving circuit. The gate driving circuit comprises a plurality of dummy stage circuits and stage circuits, which supply gate signals to each gate line and comprise a Q node, a QH node, and a QB node. A gate signal output circuit included in each of the stage circuits can output first to j-th gate signals based on first to j-th scan clock signals or a first low voltage according to the voltage level of the Q node or the voltage level of the QB node.</description><language>eng</language><subject>ADVERTISING ; ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION ; CRYPTOGRAPHY ; DISPLAY ; EDUCATION ; PHYSICS ; SEALS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241128&amp;DB=EPODOC&amp;CC=US&amp;NR=2024395216A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241128&amp;DB=EPODOC&amp;CC=US&amp;NR=2024395216A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHOI, Jaeyi</creatorcontrib><creatorcontrib>YUN, Seongho</creatorcontrib><creatorcontrib>CHOI, SooHong</creatorcontrib><title>GATE DRIVING CIRCUIT AND DISPLAY DEVICE INCLUDING GATE DRIVING CIRCUIT</title><description>The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit, and more particularly, to a gate driving circuit having a reduced size and a display device including the gate driving circuit. The gate driving circuit comprises a plurality of dummy stage circuits and stage circuits, which supply gate signals to each gate line and comprise a Q node, a QH node, and a QB node. A gate signal output circuit included in each of the stage circuits can output first to j-th gate signals based on first to j-th scan clock signals or a first low voltage according to the voltage level of the Q node or the voltage level of the QB node.</description><subject>ADVERTISING</subject><subject>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</subject><subject>CRYPTOGRAPHY</subject><subject>DISPLAY</subject><subject>EDUCATION</subject><subject>PHYSICS</subject><subject>SEALS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHBzdwxxVXAJ8gzz9HNXcPYMcg71DFFw9HNRcPEMDvBxjFRwcQ3zdHZV8PRz9gl1ASnCpoOHgTUtMac4lRdKczMou7mGOHvophbkx6cWFyQmp-allsSHBhsZGJkYW5oaGZo5GhoTpwoAQG4tCQ</recordid><startdate>20241128</startdate><enddate>20241128</enddate><creator>CHOI, Jaeyi</creator><creator>YUN, Seongho</creator><creator>CHOI, SooHong</creator><scope>EVB</scope></search><sort><creationdate>20241128</creationdate><title>GATE DRIVING CIRCUIT AND DISPLAY DEVICE INCLUDING GATE DRIVING CIRCUIT</title><author>CHOI, Jaeyi ; YUN, Seongho ; CHOI, SooHong</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024395216A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>ADVERTISING</topic><topic>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</topic><topic>CRYPTOGRAPHY</topic><topic>DISPLAY</topic><topic>EDUCATION</topic><topic>PHYSICS</topic><topic>SEALS</topic><toplevel>online_resources</toplevel><creatorcontrib>CHOI, Jaeyi</creatorcontrib><creatorcontrib>YUN, Seongho</creatorcontrib><creatorcontrib>CHOI, SooHong</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHOI, Jaeyi</au><au>YUN, Seongho</au><au>CHOI, SooHong</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>GATE DRIVING CIRCUIT AND DISPLAY DEVICE INCLUDING GATE DRIVING CIRCUIT</title><date>2024-11-28</date><risdate>2024</risdate><abstract>The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit, and more particularly, to a gate driving circuit having a reduced size and a display device including the gate driving circuit. The gate driving circuit comprises a plurality of dummy stage circuits and stage circuits, which supply gate signals to each gate line and comprise a Q node, a QH node, and a QB node. A gate signal output circuit included in each of the stage circuits can output first to j-th gate signals based on first to j-th scan clock signals or a first low voltage according to the voltage level of the Q node or the voltage level of the QB node.</abstract><oa>free_for_read</oa></addata></record>
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subjects ADVERTISING
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION
CRYPTOGRAPHY
DISPLAY
EDUCATION
PHYSICS
SEALS
title GATE DRIVING CIRCUIT AND DISPLAY DEVICE INCLUDING GATE DRIVING CIRCUIT
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-12T02%3A55%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHOI,%20Jaeyi&rft.date=2024-11-28&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024395216A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true