METHOD AND SYSTEM FOR LATCH-UP PREVENTION
An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan a...
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| creator | Chen, Wen-Hao Scott, David Barry Chen, Kuo-Ji Ying, Shu-Yi Islam, Rabiul Lin, Wun-Jie Su, Yu-Ti Lai, Po-Chia Rusu, Stefan Li, Kuan-Te |
| description | An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations. |
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| subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING |
| title | METHOD AND SYSTEM FOR LATCH-UP PREVENTION |
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