SCALABLE, OPTIMAL RETIMING OF MULTI-CLOCKED NETLISTS

Embodiments of the present disclosure provide enhanced systems and methods for implementing enhanced retiming of multiple clock netlists to improve integrated circuit (IC) design quality and provide enhanced retiming with reduced retiming runtime. Disclosed embodiments provide effective and efficien...

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Hauptverfasser:	KANZELMAN, Robert Lowell, DUREJA, Rohit, BAUMGARTNER, Jason Raymond, GAJAVELLY, Raj Kumar
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	KANZELMAN, Robert Lowell DUREJA, Rohit BAUMGARTNER, Jason Raymond GAJAVELLY, Raj Kumar
description	Embodiments of the present disclosure provide enhanced systems and methods for implementing enhanced retiming of multiple clock netlists to improve integrated circuit (IC) design quality and provide enhanced retiming with reduced retiming runtime. Disclosed embodiments provide effective and efficient retiming without sacrificing netlist quality, and yield significant speedup of retiming runtime over traditional retiming.
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title	SCALABLE, OPTIMAL RETIMING OF MULTI-CLOCKED NETLISTS
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