MEMORY, METHOD FOR MANUFACTURING MEMORY, AND ELECTRONIC DEVICE

Disclosed is a memory, a method for manufacturing the memory. The memory includes: one or more layers of memory cell arrays stacked in a direction perpendicular to a substrate; a plurality of wordlines that penetrate through one or more layers of the memory cell arrays; and a plurality of bitlines,...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: GUI, Wenhua, DAI, Jin, WANG, Xiangsheng, ZHAO, Chao, AI, Xuezheng, WANG, Guilei
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator GUI, Wenhua
DAI, Jin
WANG, Xiangsheng
ZHAO, Chao
AI, Xuezheng
WANG, Guilei
description Disclosed is a memory, a method for manufacturing the memory. The memory includes: one or more layers of memory cell arrays stacked in a direction perpendicular to a substrate; a plurality of wordlines that penetrate through one or more layers of the memory cell arrays; and a plurality of bitlines, wherein each memory cell includes a semiconductor layer that surrounds a sidewall of the wordline and extends along the sidewall and each bitline is connected to the semiconductor layers of a column of memory cells in one layer of the memory cell array, wherein the bitline is composed of different branch lines, and the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of the region of the second branch line between the two adjacent first branch lines.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024381626A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024381626A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024381626A13</originalsourceid><addsrcrecordid>eNrjZLDzdfX1D4rUUfB1DfHwd1Fw8w9S8HX0C3VzdA4JDfL0c1eAKXD0c1Fw9XF1Dgny9_N0VnBxDfN0duVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRibGFoZmRmaOhsbEqQIA858q7g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MEMORY, METHOD FOR MANUFACTURING MEMORY, AND ELECTRONIC DEVICE</title><source>esp@cenet</source><creator>GUI, Wenhua ; DAI, Jin ; WANG, Xiangsheng ; ZHAO, Chao ; AI, Xuezheng ; WANG, Guilei</creator><creatorcontrib>GUI, Wenhua ; DAI, Jin ; WANG, Xiangsheng ; ZHAO, Chao ; AI, Xuezheng ; WANG, Guilei</creatorcontrib><description>Disclosed is a memory, a method for manufacturing the memory. The memory includes: one or more layers of memory cell arrays stacked in a direction perpendicular to a substrate; a plurality of wordlines that penetrate through one or more layers of the memory cell arrays; and a plurality of bitlines, wherein each memory cell includes a semiconductor layer that surrounds a sidewall of the wordline and extends along the sidewall and each bitline is connected to the semiconductor layers of a column of memory cells in one layer of the memory cell array, wherein the bitline is composed of different branch lines, and the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of the region of the second branch line between the two adjacent first branch lines.</description><language>eng</language><subject>ELECTRICITY</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241114&amp;DB=EPODOC&amp;CC=US&amp;NR=2024381626A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25544,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241114&amp;DB=EPODOC&amp;CC=US&amp;NR=2024381626A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GUI, Wenhua</creatorcontrib><creatorcontrib>DAI, Jin</creatorcontrib><creatorcontrib>WANG, Xiangsheng</creatorcontrib><creatorcontrib>ZHAO, Chao</creatorcontrib><creatorcontrib>AI, Xuezheng</creatorcontrib><creatorcontrib>WANG, Guilei</creatorcontrib><title>MEMORY, METHOD FOR MANUFACTURING MEMORY, AND ELECTRONIC DEVICE</title><description>Disclosed is a memory, a method for manufacturing the memory. The memory includes: one or more layers of memory cell arrays stacked in a direction perpendicular to a substrate; a plurality of wordlines that penetrate through one or more layers of the memory cell arrays; and a plurality of bitlines, wherein each memory cell includes a semiconductor layer that surrounds a sidewall of the wordline and extends along the sidewall and each bitline is connected to the semiconductor layers of a column of memory cells in one layer of the memory cell array, wherein the bitline is composed of different branch lines, and the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of the region of the second branch line between the two adjacent first branch lines.</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDzdfX1D4rUUfB1DfHwd1Fw8w9S8HX0C3VzdA4JDfL0c1eAKXD0c1Fw9XF1Dgny9_N0VnBxDfN0duVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRibGFoZmRmaOhsbEqQIA858q7g</recordid><startdate>20241114</startdate><enddate>20241114</enddate><creator>GUI, Wenhua</creator><creator>DAI, Jin</creator><creator>WANG, Xiangsheng</creator><creator>ZHAO, Chao</creator><creator>AI, Xuezheng</creator><creator>WANG, Guilei</creator><scope>EVB</scope></search><sort><creationdate>20241114</creationdate><title>MEMORY, METHOD FOR MANUFACTURING MEMORY, AND ELECTRONIC DEVICE</title><author>GUI, Wenhua ; DAI, Jin ; WANG, Xiangsheng ; ZHAO, Chao ; AI, Xuezheng ; WANG, Guilei</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024381626A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>GUI, Wenhua</creatorcontrib><creatorcontrib>DAI, Jin</creatorcontrib><creatorcontrib>WANG, Xiangsheng</creatorcontrib><creatorcontrib>ZHAO, Chao</creatorcontrib><creatorcontrib>AI, Xuezheng</creatorcontrib><creatorcontrib>WANG, Guilei</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GUI, Wenhua</au><au>DAI, Jin</au><au>WANG, Xiangsheng</au><au>ZHAO, Chao</au><au>AI, Xuezheng</au><au>WANG, Guilei</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MEMORY, METHOD FOR MANUFACTURING MEMORY, AND ELECTRONIC DEVICE</title><date>2024-11-14</date><risdate>2024</risdate><abstract>Disclosed is a memory, a method for manufacturing the memory. The memory includes: one or more layers of memory cell arrays stacked in a direction perpendicular to a substrate; a plurality of wordlines that penetrate through one or more layers of the memory cell arrays; and a plurality of bitlines, wherein each memory cell includes a semiconductor layer that surrounds a sidewall of the wordline and extends along the sidewall and each bitline is connected to the semiconductor layers of a column of memory cells in one layer of the memory cell array, wherein the bitline is composed of different branch lines, and the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of the region of the second branch line between the two adjacent first branch lines.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2024381626A1
source esp@cenet
subjects ELECTRICITY
title MEMORY, METHOD FOR MANUFACTURING MEMORY, AND ELECTRONIC DEVICE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-27T23%3A46%3A48IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=GUI,%20Wenhua&rft.date=2024-11-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024381626A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true