CHECKERBOARD DUMMY DESIGN FOR EPITAXIAL OPEN RATIO
Some embodiments relate to an integrated chip structure. The integrated chip structure includes a substrate having a first device region and a second device region. A plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions...
Gespeichert in:
| Hauptverfasser: | , , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Liu, Szu-Hsien Jong, Yu-Chang Tsai, Tsung-Chieh Chou, Chien-Chih Yuan, Huan-Chih Chen, Yi-Huan Song, Jhu-Min |
| description | Some embodiments relate to an integrated chip structure. The integrated chip structure includes a substrate having a first device region and a second device region. A plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions disposed on opposing sides of a first gate structure. The epitaxial source/drain regions have an epitaxial material. A plurality of second transistor devices are disposed in the second device region and respectively include implanted source/drain regions disposed on opposing sides of a second gate structure. A dummy region includes one or more dummy structures. The one or more dummy structures have dummy epitaxial regions including the epitaxial material. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024379664A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024379664A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024379664A13</originalsourceid><addsrcrecordid>eNrjZDBy9nB19nYNcvJ3DHJRcAn19Y1UcHEN9nT3U3DzD1JwDfAMcYzwdPRR8A9w9VMIcgzx9OdhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRibG5pZmZiaOhsbEqQIACuMnvw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CHECKERBOARD DUMMY DESIGN FOR EPITAXIAL OPEN RATIO</title><source>esp@cenet</source><creator>Liu, Szu-Hsien ; Jong, Yu-Chang ; Tsai, Tsung-Chieh ; Chou, Chien-Chih ; Yuan, Huan-Chih ; Chen, Yi-Huan ; Song, Jhu-Min</creator><creatorcontrib>Liu, Szu-Hsien ; Jong, Yu-Chang ; Tsai, Tsung-Chieh ; Chou, Chien-Chih ; Yuan, Huan-Chih ; Chen, Yi-Huan ; Song, Jhu-Min</creatorcontrib><description>Some embodiments relate to an integrated chip structure. The integrated chip structure includes a substrate having a first device region and a second device region. A plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions disposed on opposing sides of a first gate structure. The epitaxial source/drain regions have an epitaxial material. A plurality of second transistor devices are disposed in the second device region and respectively include implanted source/drain regions disposed on opposing sides of a second gate structure. A dummy region includes one or more dummy structures. The one or more dummy structures have dummy epitaxial regions including the epitaxial material.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241114&DB=EPODOC&CC=US&NR=2024379664A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241114&DB=EPODOC&CC=US&NR=2024379664A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Liu, Szu-Hsien</creatorcontrib><creatorcontrib>Jong, Yu-Chang</creatorcontrib><creatorcontrib>Tsai, Tsung-Chieh</creatorcontrib><creatorcontrib>Chou, Chien-Chih</creatorcontrib><creatorcontrib>Yuan, Huan-Chih</creatorcontrib><creatorcontrib>Chen, Yi-Huan</creatorcontrib><creatorcontrib>Song, Jhu-Min</creatorcontrib><title>CHECKERBOARD DUMMY DESIGN FOR EPITAXIAL OPEN RATIO</title><description>Some embodiments relate to an integrated chip structure. The integrated chip structure includes a substrate having a first device region and a second device region. A plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions disposed on opposing sides of a first gate structure. The epitaxial source/drain regions have an epitaxial material. A plurality of second transistor devices are disposed in the second device region and respectively include implanted source/drain regions disposed on opposing sides of a second gate structure. A dummy region includes one or more dummy structures. The one or more dummy structures have dummy epitaxial regions including the epitaxial material.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDBy9nB19nYNcvJ3DHJRcAn19Y1UcHEN9nT3U3DzD1JwDfAMcYzwdPRR8A9w9VMIcgzx9OdhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRibG5pZmZiaOhsbEqQIACuMnvw</recordid><startdate>20241114</startdate><enddate>20241114</enddate><creator>Liu, Szu-Hsien</creator><creator>Jong, Yu-Chang</creator><creator>Tsai, Tsung-Chieh</creator><creator>Chou, Chien-Chih</creator><creator>Yuan, Huan-Chih</creator><creator>Chen, Yi-Huan</creator><creator>Song, Jhu-Min</creator><scope>EVB</scope></search><sort><creationdate>20241114</creationdate><title>CHECKERBOARD DUMMY DESIGN FOR EPITAXIAL OPEN RATIO</title><author>Liu, Szu-Hsien ; Jong, Yu-Chang ; Tsai, Tsung-Chieh ; Chou, Chien-Chih ; Yuan, Huan-Chih ; Chen, Yi-Huan ; Song, Jhu-Min</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024379664A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Liu, Szu-Hsien</creatorcontrib><creatorcontrib>Jong, Yu-Chang</creatorcontrib><creatorcontrib>Tsai, Tsung-Chieh</creatorcontrib><creatorcontrib>Chou, Chien-Chih</creatorcontrib><creatorcontrib>Yuan, Huan-Chih</creatorcontrib><creatorcontrib>Chen, Yi-Huan</creatorcontrib><creatorcontrib>Song, Jhu-Min</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Liu, Szu-Hsien</au><au>Jong, Yu-Chang</au><au>Tsai, Tsung-Chieh</au><au>Chou, Chien-Chih</au><au>Yuan, Huan-Chih</au><au>Chen, Yi-Huan</au><au>Song, Jhu-Min</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CHECKERBOARD DUMMY DESIGN FOR EPITAXIAL OPEN RATIO</title><date>2024-11-14</date><risdate>2024</risdate><abstract>Some embodiments relate to an integrated chip structure. The integrated chip structure includes a substrate having a first device region and a second device region. A plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions disposed on opposing sides of a first gate structure. The epitaxial source/drain regions have an epitaxial material. A plurality of second transistor devices are disposed in the second device region and respectively include implanted source/drain regions disposed on opposing sides of a second gate structure. A dummy region includes one or more dummy structures. The one or more dummy structures have dummy epitaxial regions including the epitaxial material.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2024379664A1 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | CHECKERBOARD DUMMY DESIGN FOR EPITAXIAL OPEN RATIO |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-05T21%3A31%3A32IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Liu,%20Szu-Hsien&rft.date=2024-11-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024379664A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |