INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME

A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive str...

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Hauptverfasser: CHENG, Chung-Liang, CHEN, Yen-Yu, BIH, Shih Wei
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CHEN, Yen-Yu
BIH, Shih Wei
description A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024379540A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024379540A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024379540A13</originalsourceid><addsrcrecordid>eNrjZDD19AtxDXL29_NzdQ5RCA4JCnUOCQ1yVXD0c1HwdQ3x8HdR8HdTcPMP8vX0c1cI8XBVCHb0deVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRibG5pamJgaOhsbEqQIAk90olw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME</title><source>esp@cenet</source><creator>CHENG, Chung-Liang ; CHEN, Yen-Yu ; BIH, Shih Wei</creator><creatorcontrib>CHENG, Chung-Liang ; CHEN, Yen-Yu ; BIH, Shih Wei</creatorcontrib><description>A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241114&amp;DB=EPODOC&amp;CC=US&amp;NR=2024379540A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241114&amp;DB=EPODOC&amp;CC=US&amp;NR=2024379540A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHENG, Chung-Liang</creatorcontrib><creatorcontrib>CHEN, Yen-Yu</creatorcontrib><creatorcontrib>BIH, Shih Wei</creatorcontrib><title>INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME</title><description>A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD19AtxDXL29_NzdQ5RCA4JCnUOCQ1yVXD0c1HwdQ3x8HdR8HdTcPMP8vX0c1cI8XBVCHb0deVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRibG5pamJgaOhsbEqQIAk90olw</recordid><startdate>20241114</startdate><enddate>20241114</enddate><creator>CHENG, Chung-Liang</creator><creator>CHEN, Yen-Yu</creator><creator>BIH, Shih Wei</creator><scope>EVB</scope></search><sort><creationdate>20241114</creationdate><title>INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME</title><author>CHENG, Chung-Liang ; CHEN, Yen-Yu ; BIH, Shih Wei</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024379540A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHENG, Chung-Liang</creatorcontrib><creatorcontrib>CHEN, Yen-Yu</creatorcontrib><creatorcontrib>BIH, Shih Wei</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHENG, Chung-Liang</au><au>CHEN, Yen-Yu</au><au>BIH, Shih Wei</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME</title><date>2024-11-14</date><risdate>2024</risdate><abstract>A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T18%3A06%3A09IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHENG,%20Chung-Liang&rft.date=2024-11-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024379540A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true