METHODS FOR FORMING CONTACT PLUGS WITH REDUCED CORROSION

METHODS FOR FORMING CONTACT PLUGS WITH REDUCED CORROSION

A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive...

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Hauptverfasser: Ou Yang, Liang-Yueh, Pai, Yueh-Ching, Wang, Yu-Sheng, Kao, Chen-Yuan, Hung, Chi-Cheng, Chiu, Yi-Wei
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator Ou Yang, Liang-Yueh
Pai, Yueh-Ching
Wang, Yu-Sheng
Kao, Chen-Yuan
Hung, Chi-Cheng
Chiu, Yi-Wei
description A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024363409A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024363409A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024363409A13</originalsourceid><addsrcrecordid>eNrjZLDwdQ3x8HcJVnDzDwJhX08_dwVnf78QR-cQhQCfUPdghXDPEA-FIFeXUGdXF6BUUJB_sKe_Hw8Da1piTnEqL5TmZlB2cw1x9tBNLciPTy0uSExOzUstiQ8NNjIwMjE2MzYxsHQ0NCZOFQAVMCmP</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHODS FOR FORMING CONTACT PLUGS WITH REDUCED CORROSION</title><source>esp@cenet</source><creator>Ou Yang, Liang-Yueh ; Pai, Yueh-Ching ; Wang, Yu-Sheng ; Kao, Chen-Yuan ; Hung, Chi-Cheng ; Chiu, Yi-Wei</creator><creatorcontrib>Ou Yang, Liang-Yueh ; Pai, Yueh-Ching ; Wang, Yu-Sheng ; Kao, Chen-Yuan ; Hung, Chi-Cheng ; Chiu, Yi-Wei</creatorcontrib><description>A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241031&amp;DB=EPODOC&amp;CC=US&amp;NR=2024363409A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241031&amp;DB=EPODOC&amp;CC=US&amp;NR=2024363409A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ou Yang, Liang-Yueh</creatorcontrib><creatorcontrib>Pai, Yueh-Ching</creatorcontrib><creatorcontrib>Wang, Yu-Sheng</creatorcontrib><creatorcontrib>Kao, Chen-Yuan</creatorcontrib><creatorcontrib>Hung, Chi-Cheng</creatorcontrib><creatorcontrib>Chiu, Yi-Wei</creatorcontrib><title>METHODS FOR FORMING CONTACT PLUGS WITH REDUCED CORROSION</title><description>A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDwdQ3x8HcJVnDzDwJhX08_dwVnf78QR-cQhQCfUPdghXDPEA-FIFeXUGdXF6BUUJB_sKe_Hw8Da1piTnEqL5TmZlB2cw1x9tBNLciPTy0uSExOzUstiQ8NNjIwMjE2MzYxsHQ0NCZOFQAVMCmP</recordid><startdate>20241031</startdate><enddate>20241031</enddate><creator>Ou Yang, Liang-Yueh</creator><creator>Pai, Yueh-Ching</creator><creator>Wang, Yu-Sheng</creator><creator>Kao, Chen-Yuan</creator><creator>Hung, Chi-Cheng</creator><creator>Chiu, Yi-Wei</creator><scope>EVB</scope></search><sort><creationdate>20241031</creationdate><title>METHODS FOR FORMING CONTACT PLUGS WITH REDUCED CORROSION</title><author>Ou Yang, Liang-Yueh ; Pai, Yueh-Ching ; Wang, Yu-Sheng ; Kao, Chen-Yuan ; Hung, Chi-Cheng ; Chiu, Yi-Wei</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024363409A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Ou Yang, Liang-Yueh</creatorcontrib><creatorcontrib>Pai, Yueh-Ching</creatorcontrib><creatorcontrib>Wang, Yu-Sheng</creatorcontrib><creatorcontrib>Kao, Chen-Yuan</creatorcontrib><creatorcontrib>Hung, Chi-Cheng</creatorcontrib><creatorcontrib>Chiu, Yi-Wei</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ou Yang, Liang-Yueh</au><au>Pai, Yueh-Ching</au><au>Wang, Yu-Sheng</au><au>Kao, Chen-Yuan</au><au>Hung, Chi-Cheng</au><au>Chiu, Yi-Wei</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHODS FOR FORMING CONTACT PLUGS WITH REDUCED CORROSION</title><date>2024-10-31</date><risdate>2024</risdate><abstract>A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title METHODS FOR FORMING CONTACT PLUGS WITH REDUCED CORROSION
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