THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A MID-STACK SOURCE LAYER AND METHODS FOR FORMING THE SAME
A memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a source layer overlying the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the...
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creator | SAKANE, Kento TSUTSUMI, Masanori MORIYAMA, Takumi TANAKA, Hiroyuki HOSODA, Naohiro |
description | A memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a source layer overlying the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the source layer, a memory opening vertically extending through the first-tier alternating stack, the source layer, and the second-tier alternating stack, a memory opening fill structure located in the memory opening and comprising a vertical stack of first memory elements and a vertical semiconductor channel vertically extending through each of the first electrically conductive layers, the source layer, and the second electrically conductive layers, and having a sidewall in contact with the source layer, and a bottom drain region in contact with a bottom portion of the vertical semiconductor channel. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024363165A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024363165A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024363165A13</originalsourceid><addsrcrecordid>eNqNi70KwjAURrs4iPoOF5wDttXul-TWBPMD-RE6lVLiJFqo748t-AAOh28439kWY5SeiAllyAblLGowZJzvQNBdcQJluU5C2SsgGCVYiMhvEFzyi9TYkQe0YomidCJA6_yKWYMoCQIa2hebx_Cc8-G3u-LYUuSS5end53kaxvzKnz6F6lSd66YumwuW9X-vL8OgNM8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A MID-STACK SOURCE LAYER AND METHODS FOR FORMING THE SAME</title><source>esp@cenet</source><creator>SAKANE, Kento ; TSUTSUMI, Masanori ; MORIYAMA, Takumi ; TANAKA, Hiroyuki ; HOSODA, Naohiro</creator><creatorcontrib>SAKANE, Kento ; TSUTSUMI, Masanori ; MORIYAMA, Takumi ; TANAKA, Hiroyuki ; HOSODA, Naohiro</creatorcontrib><description>A memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a source layer overlying the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the source layer, a memory opening vertically extending through the first-tier alternating stack, the source layer, and the second-tier alternating stack, a memory opening fill structure located in the memory opening and comprising a vertical stack of first memory elements and a vertical semiconductor channel vertically extending through each of the first electrically conductive layers, the source layer, and the second electrically conductive layers, and having a sidewall in contact with the source layer, and a bottom drain region in contact with a bottom portion of the vertical semiconductor channel.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241031&DB=EPODOC&CC=US&NR=2024363165A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241031&DB=EPODOC&CC=US&NR=2024363165A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SAKANE, Kento</creatorcontrib><creatorcontrib>TSUTSUMI, Masanori</creatorcontrib><creatorcontrib>MORIYAMA, Takumi</creatorcontrib><creatorcontrib>TANAKA, Hiroyuki</creatorcontrib><creatorcontrib>HOSODA, Naohiro</creatorcontrib><title>THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A MID-STACK SOURCE LAYER AND METHODS FOR FORMING THE SAME</title><description>A memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a source layer overlying the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the source layer, a memory opening vertically extending through the first-tier alternating stack, the source layer, and the second-tier alternating stack, a memory opening fill structure located in the memory opening and comprising a vertical stack of first memory elements and a vertical semiconductor channel vertically extending through each of the first electrically conductive layers, the source layer, and the second electrically conductive layers, and having a sidewall in contact with the source layer, and a bottom drain region in contact with a bottom portion of the vertical semiconductor channel.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNi70KwjAURrs4iPoOF5wDttXul-TWBPMD-RE6lVLiJFqo748t-AAOh28439kWY5SeiAllyAblLGowZJzvQNBdcQJluU5C2SsgGCVYiMhvEFzyi9TYkQe0YomidCJA6_yKWYMoCQIa2hebx_Cc8-G3u-LYUuSS5end53kaxvzKnz6F6lSd66YumwuW9X-vL8OgNM8</recordid><startdate>20241031</startdate><enddate>20241031</enddate><creator>SAKANE, Kento</creator><creator>TSUTSUMI, Masanori</creator><creator>MORIYAMA, Takumi</creator><creator>TANAKA, Hiroyuki</creator><creator>HOSODA, Naohiro</creator><scope>EVB</scope></search><sort><creationdate>20241031</creationdate><title>THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A MID-STACK SOURCE LAYER AND METHODS FOR FORMING THE SAME</title><author>SAKANE, Kento ; TSUTSUMI, Masanori ; MORIYAMA, Takumi ; TANAKA, Hiroyuki ; HOSODA, Naohiro</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024363165A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>SAKANE, Kento</creatorcontrib><creatorcontrib>TSUTSUMI, Masanori</creatorcontrib><creatorcontrib>MORIYAMA, Takumi</creatorcontrib><creatorcontrib>TANAKA, Hiroyuki</creatorcontrib><creatorcontrib>HOSODA, Naohiro</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SAKANE, Kento</au><au>TSUTSUMI, Masanori</au><au>MORIYAMA, Takumi</au><au>TANAKA, Hiroyuki</au><au>HOSODA, Naohiro</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A MID-STACK SOURCE LAYER AND METHODS FOR FORMING THE SAME</title><date>2024-10-31</date><risdate>2024</risdate><abstract>A memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a source layer overlying the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the source layer, a memory opening vertically extending through the first-tier alternating stack, the source layer, and the second-tier alternating stack, a memory opening fill structure located in the memory opening and comprising a vertical stack of first memory elements and a vertical semiconductor channel vertically extending through each of the first electrically conductive layers, the source layer, and the second electrically conductive layers, and having a sidewall in contact with the source layer, and a bottom drain region in contact with a bottom portion of the vertical semiconductor channel.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES |
title | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A MID-STACK SOURCE LAYER AND METHODS FOR FORMING THE SAME |
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