SHORT CIRCUIT DETECTION IN A READ/WRITE ASSIST CAPACITOR OF A MEMORY

An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) array including a conductive line and an assist circuit having a boost capacitor coupled to boost a voltage on the...

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Hauptverfasser: Kachir, Elazar, Shimanovich, Klimentiy, He, Bishan, Chidambarrao, Dureseti, Ogino, Atsushi, Li, Baozhen, Jungmann, Noam, Joshi, Rajiv
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creator Kachir, Elazar
Shimanovich, Klimentiy
He, Bishan
Chidambarrao, Dureseti
Ogino, Atsushi
Li, Baozhen
Jungmann, Noam
Joshi, Rajiv
description An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) array including a conductive line and an assist circuit having a boost capacitor coupled to boost a voltage on the conductive line. The boost capacitor includes first and second plates. The integrated circuit further includes a sense circuit having an input coupled to one of the first and second plates of the boost capacitor and an output and a sample circuit coupled to the output of the sense circuit. The sample circuit is configured to detect a short circuit in the boost capacitor based on a state change at the output of the sense circuit.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024355382A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024355382A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024355382A13</originalsourceid><addsrcrecordid>eNrjZHAJ9vAPClFw9gxyDvUMUXBxDXF1DvH091Pw9FNwVAhydXTRDw_yDHFVcAwO9gwGKnQMcHT2DPEPUvB3AyrwdfX1D4rkYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkYmxqamxhZGjobGxKkCAOg8LG8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SHORT CIRCUIT DETECTION IN A READ/WRITE ASSIST CAPACITOR OF A MEMORY</title><source>esp@cenet</source><creator>Kachir, Elazar ; Shimanovich, Klimentiy ; He, Bishan ; Chidambarrao, Dureseti ; Ogino, Atsushi ; Li, Baozhen ; Jungmann, Noam ; Joshi, Rajiv</creator><creatorcontrib>Kachir, Elazar ; Shimanovich, Klimentiy ; He, Bishan ; Chidambarrao, Dureseti ; Ogino, Atsushi ; Li, Baozhen ; Jungmann, Noam ; Joshi, Rajiv</creatorcontrib><description>An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) array including a conductive line and an assist circuit having a boost capacitor coupled to boost a voltage on the conductive line. The boost capacitor includes first and second plates. The integrated circuit further includes a sense circuit having an input coupled to one of the first and second plates of the boost capacitor and an output and a sample circuit coupled to the output of the sense circuit. The sample circuit is configured to detect a short circuit in the boost capacitor based on a state change at the output of the sense circuit.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241024&amp;DB=EPODOC&amp;CC=US&amp;NR=2024355382A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25551,76302</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241024&amp;DB=EPODOC&amp;CC=US&amp;NR=2024355382A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kachir, Elazar</creatorcontrib><creatorcontrib>Shimanovich, Klimentiy</creatorcontrib><creatorcontrib>He, Bishan</creatorcontrib><creatorcontrib>Chidambarrao, Dureseti</creatorcontrib><creatorcontrib>Ogino, Atsushi</creatorcontrib><creatorcontrib>Li, Baozhen</creatorcontrib><creatorcontrib>Jungmann, Noam</creatorcontrib><creatorcontrib>Joshi, Rajiv</creatorcontrib><title>SHORT CIRCUIT DETECTION IN A READ/WRITE ASSIST CAPACITOR OF A MEMORY</title><description>An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) array including a conductive line and an assist circuit having a boost capacitor coupled to boost a voltage on the conductive line. The boost capacitor includes first and second plates. The integrated circuit further includes a sense circuit having an input coupled to one of the first and second plates of the boost capacitor and an output and a sample circuit coupled to the output of the sense circuit. The sample circuit is configured to detect a short circuit in the boost capacitor based on a state change at the output of the sense circuit.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAJ9vAPClFw9gxyDvUMUXBxDXF1DvH091Pw9FNwVAhydXTRDw_yDHFVcAwO9gwGKnQMcHT2DPEPUvB3AyrwdfX1D4rkYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkYmxqamxhZGjobGxKkCAOg8LG8</recordid><startdate>20241024</startdate><enddate>20241024</enddate><creator>Kachir, Elazar</creator><creator>Shimanovich, Klimentiy</creator><creator>He, Bishan</creator><creator>Chidambarrao, Dureseti</creator><creator>Ogino, Atsushi</creator><creator>Li, Baozhen</creator><creator>Jungmann, Noam</creator><creator>Joshi, Rajiv</creator><scope>EVB</scope></search><sort><creationdate>20241024</creationdate><title>SHORT CIRCUIT DETECTION IN A READ/WRITE ASSIST CAPACITOR OF A MEMORY</title><author>Kachir, Elazar ; Shimanovich, Klimentiy ; He, Bishan ; Chidambarrao, Dureseti ; Ogino, Atsushi ; Li, Baozhen ; Jungmann, Noam ; Joshi, Rajiv</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024355382A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Kachir, Elazar</creatorcontrib><creatorcontrib>Shimanovich, Klimentiy</creatorcontrib><creatorcontrib>He, Bishan</creatorcontrib><creatorcontrib>Chidambarrao, Dureseti</creatorcontrib><creatorcontrib>Ogino, Atsushi</creatorcontrib><creatorcontrib>Li, Baozhen</creatorcontrib><creatorcontrib>Jungmann, Noam</creatorcontrib><creatorcontrib>Joshi, Rajiv</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kachir, Elazar</au><au>Shimanovich, Klimentiy</au><au>He, Bishan</au><au>Chidambarrao, Dureseti</au><au>Ogino, Atsushi</au><au>Li, Baozhen</au><au>Jungmann, Noam</au><au>Joshi, Rajiv</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SHORT CIRCUIT DETECTION IN A READ/WRITE ASSIST CAPACITOR OF A MEMORY</title><date>2024-10-24</date><risdate>2024</risdate><abstract>An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) array including a conductive line and an assist circuit having a boost capacitor coupled to boost a voltage on the conductive line. The boost capacitor includes first and second plates. The integrated circuit further includes a sense circuit having an input coupled to one of the first and second plates of the boost capacitor and an output and a sample circuit coupled to the output of the sense circuit. The sample circuit is configured to detect a short circuit in the boost capacitor based on a state change at the output of the sense circuit.</abstract><oa>free_for_read</oa></addata></record>
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subjects INFORMATION STORAGE
PHYSICS
STATIC STORES
title SHORT CIRCUIT DETECTION IN A READ/WRITE ASSIST CAPACITOR OF A MEMORY
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