ELECTRONIC CIRCUIT FOR DRIVING A QUANTUM CIRCUIT AND ASSOCIATED QUANTUM COMPUTER
The circuit is connected to the quantum circuit by bias lines and includes a digital-to-analog converter-DAC delivering an analog voltage (Ve); memory cells, connected in parallel at the output of the DAC, each memory cell including a switch (I1, I2, I3, I4) and a capacitor (C1, C2, C3, C4), the cap...
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creator | BILLIOT, Gérard JADOT, Baptiste THONNART, Yvain |
description | The circuit is connected to the quantum circuit by bias lines and includes a digital-to-analog converter-DAC delivering an analog voltage (Ve); memory cells, connected in parallel at the output of the DAC, each memory cell including a switch (I1, I2, I3, I4) and a capacitor (C1, C2, C3, C4), the capacitor storing a level of potential at which to maintain a bias line connected to the output of the memory cell; and, a device for generating control signals generating, in synchronization with the DAC, a control signal for each switch of each memory cell, the control signal, a value of the capacitor of a memory cell being selected so as to make negligible a parasitic capacitor affecting the bias line connected to said memory cell and which runs parallel to a neighboring bias line. |
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memory cells, connected in parallel at the output of the DAC, each memory cell including a switch (I1, I2, I3, I4) and a capacitor (C1, C2, C3, C4), the capacitor storing a level of potential at which to maintain a bias line connected to the output of the memory cell; and, a device for generating control signals generating, in synchronization with the DAC, a control signal for each switch of each memory cell, the control signal, a value of the capacitor of a memory cell being selected so as to make negligible a parasitic capacitor affecting the bias line connected to said memory cell and which runs parallel to a neighboring bias line.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; CODE CONVERSION IN GENERAL ; CODING ; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS ; COMPUTING ; COUNTING ; DECODING ; ELECTRICITY ; PHYSICS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241024&DB=EPODOC&CC=US&NR=2024354623A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241024&DB=EPODOC&CC=US&NR=2024354623A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BILLIOT, Gérard</creatorcontrib><creatorcontrib>JADOT, Baptiste</creatorcontrib><creatorcontrib>THONNART, Yvain</creatorcontrib><title>ELECTRONIC CIRCUIT FOR DRIVING A QUANTUM CIRCUIT AND ASSOCIATED QUANTUM COMPUTER</title><description>The circuit is connected to the quantum circuit by bias lines and includes a digital-to-analog converter-DAC delivering an analog voltage (Ve); memory cells, connected in parallel at the output of the DAC, each memory cell including a switch (I1, I2, I3, I4) and a capacitor (C1, C2, C3, C4), the capacitor storing a level of potential at which to maintain a bias line connected to the output of the memory cell; and, a device for generating control signals generating, in synchronization with the DAC, a control signal for each switch of each memory cell, the control signal, a value of the capacitor of a memory cell being selected so as to make negligible a parasitic capacitor affecting the bias line connected to said memory cell and which runs parallel to a neighboring bias line.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>CODE CONVERSION IN GENERAL</subject><subject>CODING</subject><subject>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>DECODING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAhw9XF1Dgny9_N0VnD2DHIO9QxRcPMPUnAJ8gzz9HNXcFQIDHX0Cwn1hcs6-rkoOAYH-zt7Ooa4uiCk_X0DQkNcg3gYWNMSc4pTeaE0N4Oym2uIs4duakF-fGpxQWJyal5qSXxosJGBkYmxqYmZkbGjoTFxqgBCcDAq</recordid><startdate>20241024</startdate><enddate>20241024</enddate><creator>BILLIOT, Gérard</creator><creator>JADOT, Baptiste</creator><creator>THONNART, Yvain</creator><scope>EVB</scope></search><sort><creationdate>20241024</creationdate><title>ELECTRONIC CIRCUIT FOR DRIVING A QUANTUM CIRCUIT AND ASSOCIATED QUANTUM COMPUTER</title><author>BILLIOT, Gérard ; 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memory cells, connected in parallel at the output of the DAC, each memory cell including a switch (I1, I2, I3, I4) and a capacitor (C1, C2, C3, C4), the capacitor storing a level of potential at which to maintain a bias line connected to the output of the memory cell; and, a device for generating control signals generating, in synchronization with the DAC, a control signal for each switch of each memory cell, the control signal, a value of the capacitor of a memory cell being selected so as to make negligible a parasitic capacitor affecting the bias line connected to said memory cell and which runs parallel to a neighboring bias line.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRONIC CIRCUITRY CALCULATING CODE CONVERSION IN GENERAL CODING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING DECODING ELECTRICITY PHYSICS |
title | ELECTRONIC CIRCUIT FOR DRIVING A QUANTUM CIRCUIT AND ASSOCIATED QUANTUM COMPUTER |
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