DYNAMIC PARITY SCHEME

DYNAMIC PARITY SCHEME

Methods, systems, and devices for a dynamic parity scheme are described. A memory system may include a memory device with multiple blocks of memory cells, where each block includes a first quantity of pages of memory cells storing data and a second quantity of pages of memory cells storing parity in...

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Hauptverfasser: Schettino, Gennaro, Porzio, Luca
Format: Patent
Sprache:eng
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CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator Schettino, Gennaro
Porzio, Luca
description Methods, systems, and devices for a dynamic parity scheme are described. A memory system may include a memory device with multiple blocks of memory cells, where each block includes a first quantity of pages of memory cells storing data and a second quantity of pages of memory cells storing parity information associated with the data. In some cases, the memory system may increase the quantity of pages in a block of memory cells storing parity information to improve a reliability of the data stored in the block of memory cells. For example, the memory system may increase the quantity of pages storing parity information at the block of memory cells after performing a threshold quantity of access operations at the block of memory cells or in response to detecting more than a threshold quantity of errors in data stored at the block of memory cells.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title DYNAMIC PARITY SCHEME
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