INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD USING ACCELERATOR DEVICE
An arithmetic operation target is input to an information processing apparatus which causes an accelerator apparatus to perform an arithmetic operation using the arithmetic operation target. The information processing apparatus performs, regarding each of a plurality of arithmetic operation elements...
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| creator | UEMATSU, Yutaka SHIMBO, Kenichi TAKAHASHI, Masayoshi ITSUJI, Hiroaki UEZONO, Takumi |
| description | An arithmetic operation target is input to an information processing apparatus which causes an accelerator apparatus to perform an arithmetic operation using the arithmetic operation target. The information processing apparatus performs, regarding each of a plurality of arithmetic operation elements of the arithmetic operation target, whether to allocate one or more diagnostic circuits, which are available processing circuits for an accuracy diagnosis of the arithmetic operation from a plurality of processing circuits in the accelerator apparatus to the arithmetic operation element on the basis of a failure influence degree. The reliability of the information processing apparatus that is used to judge whether or not to continue an action(s) of the information processing apparatus is calculated on the basis of the number of arithmetic operation elements of the arithmetic operation target, the number of arithmetic operation elements to which at least one diagnostic circuit is allocated, and the failure influence degree. |
| format | Patent |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD USING ACCELERATOR DEVICE |
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