SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the fi...
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creator | Jeong, KooWoong Kim, Byong Jin Shin, Min Chul Lee, Jae Ung Choi, Wook Lee, Yung Woo Kim, Chang Hun Kim, Ji Hyun Cho, EunNaRa Bang, Dong Hyun Lim, Ho Jeong |
description | A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024332159A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024332159A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024332159A13</originalsourceid><addsrcrecordid>eNrjZDALdvX1dPb3cwl1DvEPUghwdPZ2dHdVcPRzUfB19At1c3QOCQ3y9HNX8HUN8fB3UQjxcA1y9XfjYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkYmxsZGhqaWjobGxKkCAL_pKO8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF</title><source>esp@cenet</source><creator>Jeong, KooWoong ; Kim, Byong Jin ; Shin, Min Chul ; Lee, Jae Ung ; Choi, Wook ; Lee, Yung Woo ; Kim, Chang Hun ; Kim, Ji Hyun ; Cho, EunNaRa ; Bang, Dong Hyun ; Lim, Ho Jeong</creator><creatorcontrib>Jeong, KooWoong ; Kim, Byong Jin ; Shin, Min Chul ; Lee, Jae Ung ; Choi, Wook ; Lee, Yung Woo ; Kim, Chang Hun ; Kim, Ji Hyun ; Cho, EunNaRa ; Bang, Dong Hyun ; Lim, Ho Jeong</creatorcontrib><description>A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241003&DB=EPODOC&CC=US&NR=2024332159A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241003&DB=EPODOC&CC=US&NR=2024332159A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Jeong, KooWoong</creatorcontrib><creatorcontrib>Kim, Byong Jin</creatorcontrib><creatorcontrib>Shin, Min Chul</creatorcontrib><creatorcontrib>Lee, Jae Ung</creatorcontrib><creatorcontrib>Choi, Wook</creatorcontrib><creatorcontrib>Lee, Yung Woo</creatorcontrib><creatorcontrib>Kim, Chang Hun</creatorcontrib><creatorcontrib>Kim, Ji Hyun</creatorcontrib><creatorcontrib>Cho, EunNaRa</creatorcontrib><creatorcontrib>Bang, Dong Hyun</creatorcontrib><creatorcontrib>Lim, Ho Jeong</creatorcontrib><title>SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF</title><description>A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDALdvX1dPb3cwl1DvEPUghwdPZ2dHdVcPRzUfB19At1c3QOCQ3y9HNX8HUN8fB3UQjxcA1y9XfjYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkYmxsZGhqaWjobGxKkCAL_pKO8</recordid><startdate>20241003</startdate><enddate>20241003</enddate><creator>Jeong, KooWoong</creator><creator>Kim, Byong Jin</creator><creator>Shin, Min Chul</creator><creator>Lee, Jae Ung</creator><creator>Choi, Wook</creator><creator>Lee, Yung Woo</creator><creator>Kim, Chang Hun</creator><creator>Kim, Ji Hyun</creator><creator>Cho, EunNaRa</creator><creator>Bang, Dong Hyun</creator><creator>Lim, Ho Jeong</creator><scope>EVB</scope></search><sort><creationdate>20241003</creationdate><title>SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF</title><author>Jeong, KooWoong ; Kim, Byong Jin ; Shin, Min Chul ; Lee, Jae Ung ; Choi, Wook ; Lee, Yung Woo ; Kim, Chang Hun ; Kim, Ji Hyun ; Cho, EunNaRa ; Bang, Dong Hyun ; Lim, Ho Jeong</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024332159A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Jeong, KooWoong</creatorcontrib><creatorcontrib>Kim, Byong Jin</creatorcontrib><creatorcontrib>Shin, Min Chul</creatorcontrib><creatorcontrib>Lee, Jae Ung</creatorcontrib><creatorcontrib>Choi, Wook</creatorcontrib><creatorcontrib>Lee, Yung Woo</creatorcontrib><creatorcontrib>Kim, Chang Hun</creatorcontrib><creatorcontrib>Kim, Ji Hyun</creatorcontrib><creatorcontrib>Cho, EunNaRa</creatorcontrib><creatorcontrib>Bang, Dong Hyun</creatorcontrib><creatorcontrib>Lim, Ho Jeong</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jeong, KooWoong</au><au>Kim, Byong Jin</au><au>Shin, Min Chul</au><au>Lee, Jae Ung</au><au>Choi, Wook</au><au>Lee, Yung Woo</au><au>Kim, Chang Hun</au><au>Kim, Ji Hyun</au><au>Cho, EunNaRa</au><au>Bang, Dong Hyun</au><au>Lim, Ho Jeong</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF</title><date>2024-10-03</date><risdate>2024</risdate><abstract>A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF |
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