SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE

A method of manufacture for a semiconductor package includes; forming a molding member on side surfaces of the semiconductor chips, using an adhesive to attach a carrier substrate to upper surfaces of the molding member and the semiconductor chips, using a first blade having a first blade-width to c...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Lee, Jongho, Park, Jinwoo, Ko, Yeongkwon
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Lee, Jongho
Park, Jinwoo
Ko, Yeongkwon
description A method of manufacture for a semiconductor package includes; forming a molding member on side surfaces of the semiconductor chips, using an adhesive to attach a carrier substrate to upper surfaces of the molding member and the semiconductor chips, using a first blade having a first blade-width to cut away selected portions of the carrier substrate and portions of the adhesive underlying the selected portions of the carrier substrate, and using the first blade to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are dispose above portions of the molding member between adjacent ones of semiconductor chips, using a second blade having a second blade-width narrower than the first blade-width to cut through a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separate a package structure including a semiconductor chip supported by a cut portion of the carrier substrate and bonding the package structure to an upper surface of a package substrate.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024321666A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024321666A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024321666A13</originalsourceid><addsrcrecordid>eNrjZNAPdvX1dPb3cwl1DvEPUghwdPZ2dHdVcPRzUfB1DfHwd1Hwd1PwdfQLdXN0DgkNcuVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRibGRoZmZmaOhsbEqQIAlvQm2Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE</title><source>esp@cenet</source><creator>Lee, Jongho ; Park, Jinwoo ; Ko, Yeongkwon</creator><creatorcontrib>Lee, Jongho ; Park, Jinwoo ; Ko, Yeongkwon</creatorcontrib><description>A method of manufacture for a semiconductor package includes; forming a molding member on side surfaces of the semiconductor chips, using an adhesive to attach a carrier substrate to upper surfaces of the molding member and the semiconductor chips, using a first blade having a first blade-width to cut away selected portions of the carrier substrate and portions of the adhesive underlying the selected portions of the carrier substrate, and using the first blade to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are dispose above portions of the molding member between adjacent ones of semiconductor chips, using a second blade having a second blade-width narrower than the first blade-width to cut through a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separate a package structure including a semiconductor chip supported by a cut portion of the carrier substrate and bonding the package structure to an upper surface of a package substrate.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240926&amp;DB=EPODOC&amp;CC=US&amp;NR=2024321666A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240926&amp;DB=EPODOC&amp;CC=US&amp;NR=2024321666A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lee, Jongho</creatorcontrib><creatorcontrib>Park, Jinwoo</creatorcontrib><creatorcontrib>Ko, Yeongkwon</creatorcontrib><title>SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE</title><description>A method of manufacture for a semiconductor package includes; forming a molding member on side surfaces of the semiconductor chips, using an adhesive to attach a carrier substrate to upper surfaces of the molding member and the semiconductor chips, using a first blade having a first blade-width to cut away selected portions of the carrier substrate and portions of the adhesive underlying the selected portions of the carrier substrate, and using the first blade to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are dispose above portions of the molding member between adjacent ones of semiconductor chips, using a second blade having a second blade-width narrower than the first blade-width to cut through a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separate a package structure including a semiconductor chip supported by a cut portion of the carrier substrate and bonding the package structure to an upper surface of a package substrate.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAPdvX1dPb3cwl1DvEPUghwdPZ2dHdVcPRzUfB1DfHwd1Hwd1PwdfQLdXN0DgkNcuVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRibGRoZmZmaOhsbEqQIAlvQm2Q</recordid><startdate>20240926</startdate><enddate>20240926</enddate><creator>Lee, Jongho</creator><creator>Park, Jinwoo</creator><creator>Ko, Yeongkwon</creator><scope>EVB</scope></search><sort><creationdate>20240926</creationdate><title>SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE</title><author>Lee, Jongho ; Park, Jinwoo ; Ko, Yeongkwon</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024321666A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Lee, Jongho</creatorcontrib><creatorcontrib>Park, Jinwoo</creatorcontrib><creatorcontrib>Ko, Yeongkwon</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lee, Jongho</au><au>Park, Jinwoo</au><au>Ko, Yeongkwon</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE</title><date>2024-09-26</date><risdate>2024</risdate><abstract>A method of manufacture for a semiconductor package includes; forming a molding member on side surfaces of the semiconductor chips, using an adhesive to attach a carrier substrate to upper surfaces of the molding member and the semiconductor chips, using a first blade having a first blade-width to cut away selected portions of the carrier substrate and portions of the adhesive underlying the selected portions of the carrier substrate, and using the first blade to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are dispose above portions of the molding member between adjacent ones of semiconductor chips, using a second blade having a second blade-width narrower than the first blade-width to cut through a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separate a package structure including a semiconductor chip supported by a cut portion of the carrier substrate and bonding the package structure to an upper surface of a package substrate.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2024321666A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-12T14%3A14%3A08IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Lee,%20Jongho&rft.date=2024-09-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024321666A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true