MEMORY SYSTEM

A memory system includes a memory and a memory controller. The memory controller includes an encoder including a first encoder configured to generate a first codeword from a plurality of first data sections. The first codeword includes a first error correction code parity for correcting errors in nu...

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Hauptverfasser:	YAMAKI, Ryo, SHIRAKAWA, Masanobu
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	YAMAKI, Ryo SHIRAKAWA, Masanobu
description	A memory system includes a memory and a memory controller. The memory controller includes an encoder including a first encoder configured to generate a first codeword from a plurality of first data sections. The first codeword includes a first error correction code parity for correcting errors in number based on a rank in the plurality of first data sections and the first codeword. The first codeword includes a plurality of first bit strings respectively associated with a plurality of columns. The first bit strings each include a plurality of bits respectively associated with a plurality of rows. The memory controller is configured to write the plurality of first bit strings into the plurality of magnetic bodies, respectively, such that the magnetic body in which one of the first bit strings is written is different.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024320091A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024320091A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024320091A13</originalsourceid><addsrcrecordid>eNrjZOD1dfX1D4pUCI4MDnH15WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGJsZGBgaWho6GxsSpAgAugB20</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MEMORY SYSTEM</title><source>esp@cenet</source><creator>YAMAKI, Ryo ; SHIRAKAWA, Masanobu</creator><creatorcontrib>YAMAKI, Ryo ; SHIRAKAWA, Masanobu</creatorcontrib><description>A memory system includes a memory and a memory controller. The memory controller includes an encoder including a first encoder configured to generate a first codeword from a plurality of first data sections. The first codeword includes a first error correction code parity for correcting errors in number based on a rank in the plurality of first data sections and the first codeword. The first codeword includes a plurality of first bit strings respectively associated with a plurality of columns. The first bit strings each include a plurality of bits respectively associated with a plurality of rows. The memory controller is configured to write the plurality of first bit strings into the plurality of magnetic bodies, respectively, such that the magnetic body in which one of the first bit strings is written is different.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240926&DB=EPODOC&CC=US&NR=2024320091A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240926&DB=EPODOC&CC=US&NR=2024320091A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YAMAKI, Ryo</creatorcontrib><creatorcontrib>SHIRAKAWA, Masanobu</creatorcontrib><title>MEMORY SYSTEM</title><description>A memory system includes a memory and a memory controller. The memory controller includes an encoder including a first encoder configured to generate a first codeword from a plurality of first data sections. The first codeword includes a first error correction code parity for correcting errors in number based on a rank in the plurality of first data sections and the first codeword. The first codeword includes a plurality of first bit strings respectively associated with a plurality of columns. The first bit strings each include a plurality of bits respectively associated with a plurality of rows. The memory controller is configured to write the plurality of first bit strings into the plurality of magnetic bodies, respectively, such that the magnetic body in which one of the first bit strings is written is different.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOD1dfX1D4pUCI4MDnH15WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGJsZGBgaWho6GxsSpAgAugB20</recordid><startdate>20240926</startdate><enddate>20240926</enddate><creator>YAMAKI, Ryo</creator><creator>SHIRAKAWA, Masanobu</creator><scope>EVB</scope></search><sort><creationdate>20240926</creationdate><title>MEMORY SYSTEM</title><author>YAMAKI, Ryo ; SHIRAKAWA, Masanobu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024320091A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>YAMAKI, Ryo</creatorcontrib><creatorcontrib>SHIRAKAWA, Masanobu</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YAMAKI, Ryo</au><au>SHIRAKAWA, Masanobu</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MEMORY SYSTEM</title><date>2024-09-26</date><risdate>2024</risdate><abstract>A memory system includes a memory and a memory controller. The memory controller includes an encoder including a first encoder configured to generate a first codeword from a plurality of first data sections. The first codeword includes a first error correction code parity for correcting errors in number based on a rank in the plurality of first data sections and the first codeword. The first codeword includes a plurality of first bit strings respectively associated with a plurality of columns. The first bit strings each include a plurality of bits respectively associated with a plurality of rows. The memory controller is configured to write the plurality of first bit strings into the plurality of magnetic bodies, respectively, such that the magnetic body in which one of the first bit strings is written is different.</abstract><oa>free_for_read</oa></addata></record>
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	MEMORY SYSTEM
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