SEMICONDUCTOR STRUCTURE WITH ISOLATION REGION INCLUDING COMBINATION OF DEEP AND SHALLOW TRENCH ISOLATION STRUCTURES AND METHOD
Disclosed is a semiconductor structure and method of forming the semiconductor structure. Specifically, the semiconductor structure can include a first semiconductor fin extending from a semiconductor substrate. The semiconductor structure can further include an isolation region on the semiconductor...
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creator | Yu, Hong Kozarsky, Eric Scott Tokranov, Anton V Mazza, James P Strehlow, Elizabeth A Vulcano Rossi, Vitor A |
description | Disclosed is a semiconductor structure and method of forming the semiconductor structure. Specifically, the semiconductor structure can include a first semiconductor fin extending from a semiconductor substrate. The semiconductor structure can further include an isolation region on the semiconductor substrate adjacent to a lower portion of the first semiconductor fin. The first semiconductor fin can, for example, be incorporated into a single-fin fin-type semiconductor device, such as a single-fin fin-type field effect transistor (FINFET). The isolation region can include at least one shallow trench isolation (STI) structure positioned laterally between and immediately adjacent to sections of a deep trench isolation (DTI) structure. With this alternating DTI-STI-DTI configuration, overall shrinkage of isolation material of the isolation region during anneals is reduced and, thus, so are stress-induced crystalline defects in the first semiconductor fin. Also disclosed are methods for forming such a semiconductor structure. |
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Specifically, the semiconductor structure can include a first semiconductor fin extending from a semiconductor substrate. The semiconductor structure can further include an isolation region on the semiconductor substrate adjacent to a lower portion of the first semiconductor fin. The first semiconductor fin can, for example, be incorporated into a single-fin fin-type semiconductor device, such as a single-fin fin-type field effect transistor (FINFET). The isolation region can include at least one shallow trench isolation (STI) structure positioned laterally between and immediately adjacent to sections of a deep trench isolation (DTI) structure. With this alternating DTI-STI-DTI configuration, overall shrinkage of isolation material of the isolation region during anneals is reduced and, thus, so are stress-induced crystalline defects in the first semiconductor fin. Also disclosed are methods for forming such a semiconductor structure.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240919&DB=EPODOC&CC=US&NR=2024313113A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240919&DB=EPODOC&CC=US&NR=2024313113A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Yu, Hong</creatorcontrib><creatorcontrib>Kozarsky, Eric Scott</creatorcontrib><creatorcontrib>Tokranov, Anton V</creatorcontrib><creatorcontrib>Mazza, James P</creatorcontrib><creatorcontrib>Strehlow, Elizabeth A</creatorcontrib><creatorcontrib>Vulcano Rossi, Vitor A</creatorcontrib><title>SEMICONDUCTOR STRUCTURE WITH ISOLATION REGION INCLUDING COMBINATION OF DEEP AND SHALLOW TRENCH ISOLATION STRUCTURES AND METHOD</title><description>Disclosed is a semiconductor structure and method of forming the semiconductor structure. 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Also disclosed are methods for forming such a semiconductor structure.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjL0KwjAURrs4iPoOF5wF0_gCaXLbBNJcyQ8dS5E4iRbq7LP7izg6nQ--w5kXt4CtkeRUkpE8hOgfI3mEzkQNJpAV0ZADj80TxkmblHENSGor494n1aAQ9yCcgqCFtdRB9Ojkb-GbDi-vxahJLYvZcThNefXholjXGKXe5PHS52kcDvmcr30K5bbcccYZ44Lx_6w7XWI9IQ</recordid><startdate>20240919</startdate><enddate>20240919</enddate><creator>Yu, Hong</creator><creator>Kozarsky, Eric Scott</creator><creator>Tokranov, Anton V</creator><creator>Mazza, James P</creator><creator>Strehlow, Elizabeth A</creator><creator>Vulcano Rossi, Vitor A</creator><scope>EVB</scope></search><sort><creationdate>20240919</creationdate><title>SEMICONDUCTOR STRUCTURE WITH ISOLATION REGION INCLUDING COMBINATION OF DEEP AND SHALLOW TRENCH ISOLATION STRUCTURES AND METHOD</title><author>Yu, Hong ; Kozarsky, Eric Scott ; Tokranov, Anton V ; Mazza, James P ; Strehlow, Elizabeth A ; Vulcano Rossi, Vitor A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024313113A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Yu, Hong</creatorcontrib><creatorcontrib>Kozarsky, Eric Scott</creatorcontrib><creatorcontrib>Tokranov, Anton V</creatorcontrib><creatorcontrib>Mazza, James P</creatorcontrib><creatorcontrib>Strehlow, Elizabeth A</creatorcontrib><creatorcontrib>Vulcano Rossi, Vitor A</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yu, Hong</au><au>Kozarsky, Eric Scott</au><au>Tokranov, Anton V</au><au>Mazza, James P</au><au>Strehlow, Elizabeth A</au><au>Vulcano Rossi, Vitor A</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR STRUCTURE WITH ISOLATION REGION INCLUDING COMBINATION OF DEEP AND SHALLOW TRENCH ISOLATION STRUCTURES AND METHOD</title><date>2024-09-19</date><risdate>2024</risdate><abstract>Disclosed is a semiconductor structure and method of forming the semiconductor structure. Specifically, the semiconductor structure can include a first semiconductor fin extending from a semiconductor substrate. The semiconductor structure can further include an isolation region on the semiconductor substrate adjacent to a lower portion of the first semiconductor fin. The first semiconductor fin can, for example, be incorporated into a single-fin fin-type semiconductor device, such as a single-fin fin-type field effect transistor (FINFET). The isolation region can include at least one shallow trench isolation (STI) structure positioned laterally between and immediately adjacent to sections of a deep trench isolation (DTI) structure. With this alternating DTI-STI-DTI configuration, overall shrinkage of isolation material of the isolation region during anneals is reduced and, thus, so are stress-induced crystalline defects in the first semiconductor fin. Also disclosed are methods for forming such a semiconductor structure.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR STRUCTURE WITH ISOLATION REGION INCLUDING COMBINATION OF DEEP AND SHALLOW TRENCH ISOLATION STRUCTURES AND METHOD |
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