Receiver with Flexible Link Synchronization

A receiver includes: a PHY layer, and a processor coupled to the PHY layer. The processor is configured to: receive a set of data bits from the PHY layer; compare the set of data bits to a sync header pattern; determine a mismatch metric responsive to the comparison and to an adjustable scaling fact...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	KRISHNA, Kandalla, VIJAYAKUMAR, Aravind, BALAKRISHNAN, Jaiganesh, RAMESH, Goutham
Format:	Patent
Sprache:	eng
Schlagworte:	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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