Receiver with Flexible Link Synchronization

Receiver with Flexible Link Synchronization

A receiver includes: a PHY layer, and a processor coupled to the PHY layer. The processor is configured to: receive a set of data bits from the PHY layer; compare the set of data bits to a sync header pattern; determine a mismatch metric responsive to the comparison and to an adjustable scaling fact...

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Hauptverfasser: KRISHNA, Kandalla, VIJAYAKUMAR, Aravind, BALAKRISHNAN, Jaiganesh, RAMESH, Goutham
Format: Patent
Sprache:eng
Schlagworte:
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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creator KRISHNA, Kandalla
VIJAYAKUMAR, Aravind
BALAKRISHNAN, Jaiganesh
RAMESH, Goutham
description A receiver includes: a PHY layer, and a processor coupled to the PHY layer. The processor is configured to: receive a set of data bits from the PHY layer; compare the set of data bits to a sync header pattern; determine a mismatch metric responsive to the comparison and to an adjustable scaling factor, and execute link synchronization operations based on the mismatch metric.
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subjects ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title Receiver with Flexible Link Synchronization
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