SPECIFYING A PROCESSOR WITH ASSURED AND OPPORTUNISTIC CORES

In one embodiment, a processor includes: a plurality of cores to execute instructions and a non-volatile storage coupled to the plurality of cores to store identification information regarding the plurality of cores, the identification information to identify, for each of the plurality of cores, the core as an assured core or an opportunistic core. The processor is specified with a first subset of the plurality of cores comprising assured cores and a second subset of the plurality of cores comprising opportunistic cores, and is to execute, within a specified power budget and a specified thermal budget, a specified workload on the first subset of the plurality of cores at a first performance level. Other embodiments are described and claimed.