INTEGRATED CIRCUIT INCLUDING BACKSIDE WIRING AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT

An integrated circuit includes a power rail extending in a first direction and configured to receive a supply voltage, a gate line below the power rail and extending in a second direction that intersects the first direction, a source/drain region adjacent to the gate line in the first direction and...

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Hauptverfasser: Do, Jungho, Kim, Wookyu, Lee, Seungmin, Kim, Changbeom
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creator Do, Jungho
Kim, Wookyu
Lee, Seungmin
Kim, Changbeom
description An integrated circuit includes a power rail extending in a first direction and configured to receive a supply voltage, a gate line below the power rail and extending in a second direction that intersects the first direction, a source/drain region adjacent to the gate line in the first direction and configured to receive the supply voltage from the power rail, a frontside wiring layer above the power rail, connected to the power rail, and configured to transmit the supply voltage to the power rail, and a backside wiring layer below the power rail, connected to the power rail, and configured to transmit the supply voltage to the power rail.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024266344A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024266344A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024266344A13</originalsourceid><addsrcrecordid>eNrjZIj29AtxdQ9yDHF1UXD2DHIO9QxR8PRz9gl18fRzV3BydPYO9nRxVQj3DALxHf1cFHxdQzz8XRT83RRcXIM93f1A4iEergqYBvEwsKYl5hSn8kJpbgZlN9cQZw_d1IL8-NTigsTk1LzUkvjQYCMDIxMjMzNjExNHQ2PiVAEANwsy0Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>INTEGRATED CIRCUIT INCLUDING BACKSIDE WIRING AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT</title><source>esp@cenet</source><creator>Do, Jungho ; Kim, Wookyu ; Lee, Seungmin ; Kim, Changbeom</creator><creatorcontrib>Do, Jungho ; Kim, Wookyu ; Lee, Seungmin ; Kim, Changbeom</creatorcontrib><description>An integrated circuit includes a power rail extending in a first direction and configured to receive a supply voltage, a gate line below the power rail and extending in a second direction that intersects the first direction, a source/drain region adjacent to the gate line in the first direction and configured to receive the supply voltage from the power rail, a frontside wiring layer above the power rail, connected to the power rail, and configured to transmit the supply voltage to the power rail, and a backside wiring layer below the power rail, connected to the power rail, and configured to transmit the supply voltage to the power rail.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240808&amp;DB=EPODOC&amp;CC=US&amp;NR=2024266344A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240808&amp;DB=EPODOC&amp;CC=US&amp;NR=2024266344A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Do, Jungho</creatorcontrib><creatorcontrib>Kim, Wookyu</creatorcontrib><creatorcontrib>Lee, Seungmin</creatorcontrib><creatorcontrib>Kim, Changbeom</creatorcontrib><title>INTEGRATED CIRCUIT INCLUDING BACKSIDE WIRING AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT</title><description>An integrated circuit includes a power rail extending in a first direction and configured to receive a supply voltage, a gate line below the power rail and extending in a second direction that intersects the first direction, a source/drain region adjacent to the gate line in the first direction and configured to receive the supply voltage from the power rail, a frontside wiring layer above the power rail, connected to the power rail, and configured to transmit the supply voltage to the power rail, and a backside wiring layer below the power rail, connected to the power rail, and configured to transmit the supply voltage to the power rail.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZIj29AtxdQ9yDHF1UXD2DHIO9QxR8PRz9gl18fRzV3BydPYO9nRxVQj3DALxHf1cFHxdQzz8XRT83RRcXIM93f1A4iEergqYBvEwsKYl5hSn8kJpbgZlN9cQZw_d1IL8-NTigsTk1LzUkvjQYCMDIxMjMzNjExNHQ2PiVAEANwsy0Q</recordid><startdate>20240808</startdate><enddate>20240808</enddate><creator>Do, Jungho</creator><creator>Kim, Wookyu</creator><creator>Lee, Seungmin</creator><creator>Kim, Changbeom</creator><scope>EVB</scope></search><sort><creationdate>20240808</creationdate><title>INTEGRATED CIRCUIT INCLUDING BACKSIDE WIRING AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT</title><author>Do, Jungho ; Kim, Wookyu ; Lee, Seungmin ; Kim, Changbeom</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024266344A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Do, Jungho</creatorcontrib><creatorcontrib>Kim, Wookyu</creatorcontrib><creatorcontrib>Lee, Seungmin</creatorcontrib><creatorcontrib>Kim, Changbeom</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Do, Jungho</au><au>Kim, Wookyu</au><au>Lee, Seungmin</au><au>Kim, Changbeom</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INTEGRATED CIRCUIT INCLUDING BACKSIDE WIRING AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT</title><date>2024-08-08</date><risdate>2024</risdate><abstract>An integrated circuit includes a power rail extending in a first direction and configured to receive a supply voltage, a gate line below the power rail and extending in a second direction that intersects the first direction, a source/drain region adjacent to the gate line in the first direction and configured to receive the supply voltage from the power rail, a frontside wiring layer above the power rail, connected to the power rail, and configured to transmit the supply voltage to the power rail, and a backside wiring layer below the power rail, connected to the power rail, and configured to transmit the supply voltage to the power rail.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title INTEGRATED CIRCUIT INCLUDING BACKSIDE WIRING AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T20%3A19%3A09IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Do,%20Jungho&rft.date=2024-08-08&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024266344A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true