TRANSISTOR DEVICE HAVING A GATE SETBACK FROM A GATE DIELECTRIC
An integrated chip including a first source/drain region and a second source/drain region in a semiconductor substrate and laterally spaced apart along a top surface of the substrate. A gate dielectric layer is over the substrate and extends laterally between the first source/drain region and the se...
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| creator | Jong, Yu-Chang Liu, Ruey-Hsin Chen, Fei-Yun Kung, Ta-Yuan Yao, Chih-Wen Albert Chu, Chen-Liang Lei, Ming-Ta |
| description | An integrated chip including a first source/drain region and a second source/drain region in a semiconductor substrate and laterally spaced apart along a top surface of the substrate. A gate dielectric layer is over the substrate and extends laterally between the first source/drain region and the second source/drain region. A thickness of the gate dielectric layer along a first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer. A trench isolation layer extends along gate dielectric layer. A first sidewall of the trench isolation layer extends along the first sidewall of the gate dielectric layer. A gate layer is directly over the gate dielectric layer and between the first source/drain region and the second source/drain region. A first sidewall of the gate layer is directly over the gate dielectric layer and laterally setback from the first sidewall of the gate dielectric layer. |
| format | Patent |
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A gate dielectric layer is over the substrate and extends laterally between the first source/drain region and the second source/drain region. A thickness of the gate dielectric layer along a first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer. A trench isolation layer extends along gate dielectric layer. A first sidewall of the trench isolation layer extends along the first sidewall of the gate dielectric layer. A gate layer is directly over the gate dielectric layer and between the first source/drain region and the second source/drain region. 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A first sidewall of the gate layer is directly over the gate dielectric layer and laterally setback from the first sidewall of the gate dielectric layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLALCXL0C_YMDvEPUnBxDfN0dlXwcAzz9HNXcFRwdwxxVQh2DXFydPZWcAvy94WJuXi6-rg6hwR5OvMwsKYl5hSn8kJpbgZlN9cQZw_d1IL8-NTigsTk1LzUkvjQYCMDIxMjUwtjc2NHQ2PiVAEAzJ0qlA</recordid><startdate>20240801</startdate><enddate>20240801</enddate><creator>Jong, Yu-Chang</creator><creator>Liu, Ruey-Hsin</creator><creator>Chen, Fei-Yun</creator><creator>Kung, Ta-Yuan</creator><creator>Yao, Chih-Wen Albert</creator><creator>Chu, Chen-Liang</creator><creator>Lei, Ming-Ta</creator><scope>EVB</scope></search><sort><creationdate>20240801</creationdate><title>TRANSISTOR DEVICE HAVING A GATE SETBACK FROM A GATE DIELECTRIC</title><author>Jong, Yu-Chang ; Liu, Ruey-Hsin ; Chen, Fei-Yun ; Kung, Ta-Yuan ; Yao, Chih-Wen Albert ; Chu, Chen-Liang ; Lei, Ming-Ta</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024258373A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Jong, Yu-Chang</creatorcontrib><creatorcontrib>Liu, Ruey-Hsin</creatorcontrib><creatorcontrib>Chen, Fei-Yun</creatorcontrib><creatorcontrib>Kung, Ta-Yuan</creatorcontrib><creatorcontrib>Yao, Chih-Wen Albert</creatorcontrib><creatorcontrib>Chu, Chen-Liang</creatorcontrib><creatorcontrib>Lei, Ming-Ta</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jong, Yu-Chang</au><au>Liu, Ruey-Hsin</au><au>Chen, Fei-Yun</au><au>Kung, Ta-Yuan</au><au>Yao, Chih-Wen Albert</au><au>Chu, Chen-Liang</au><au>Lei, Ming-Ta</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>TRANSISTOR DEVICE HAVING A GATE SETBACK FROM A GATE DIELECTRIC</title><date>2024-08-01</date><risdate>2024</risdate><abstract>An integrated chip including a first source/drain region and a second source/drain region in a semiconductor substrate and laterally spaced apart along a top surface of the substrate. A gate dielectric layer is over the substrate and extends laterally between the first source/drain region and the second source/drain region. A thickness of the gate dielectric layer along a first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer. A trench isolation layer extends along gate dielectric layer. A first sidewall of the trench isolation layer extends along the first sidewall of the gate dielectric layer. A gate layer is directly over the gate dielectric layer and between the first source/drain region and the second source/drain region. A first sidewall of the gate layer is directly over the gate dielectric layer and laterally setback from the first sidewall of the gate dielectric layer.</abstract><oa>free_for_read</oa></addata></record> |
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| title | TRANSISTOR DEVICE HAVING A GATE SETBACK FROM A GATE DIELECTRIC |
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