DATA PREFETCHING FOR GRAPHICS DATA PROCESSING
Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches in...
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| creator | Anantaraman, Aravindh Insko, Brent Kim, Sungye Galoppo von Borries, Nicolas Ranganathan, Vasanth Surti, Prasoonkumar Striramassarma, Lakshminarayanan Pearce, Jonathan Appu, Abhishek R Ould-Ahmed-Vall, ElMoustapha Vemulapalli, Vikranth Koker, Altug Hunter, Jr., Arthur Ashbaugh, Ben Sinha, Kamal Ray, Joydeep MacPherson, Mike Sadler, William B Andrei, Valentin Ramadoss, Murali Maiyuran, Subramaniam Janus, Scott |
| description | Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the Li cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache. |
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An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the Li cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ; PHYSICS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240801&DB=EPODOC&CC=US&NR=2024256456A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240801&DB=EPODOC&CC=US&NR=2024256456A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Anantaraman, Aravindh</creatorcontrib><creatorcontrib>Insko, Brent</creatorcontrib><creatorcontrib>Kim, Sungye</creatorcontrib><creatorcontrib>Galoppo von Borries, Nicolas</creatorcontrib><creatorcontrib>Ranganathan, Vasanth</creatorcontrib><creatorcontrib>Surti, Prasoonkumar</creatorcontrib><creatorcontrib>Striramassarma, Lakshminarayanan</creatorcontrib><creatorcontrib>Pearce, Jonathan</creatorcontrib><creatorcontrib>Appu, Abhishek R</creatorcontrib><creatorcontrib>Ould-Ahmed-Vall, ElMoustapha</creatorcontrib><creatorcontrib>Vemulapalli, Vikranth</creatorcontrib><creatorcontrib>Koker, Altug</creatorcontrib><creatorcontrib>Hunter, Jr., Arthur</creatorcontrib><creatorcontrib>Ashbaugh, Ben</creatorcontrib><creatorcontrib>Sinha, Kamal</creatorcontrib><creatorcontrib>Ray, Joydeep</creatorcontrib><creatorcontrib>MacPherson, Mike</creatorcontrib><creatorcontrib>Sadler, William B</creatorcontrib><creatorcontrib>Andrei, Valentin</creatorcontrib><creatorcontrib>Ramadoss, Murali</creatorcontrib><creatorcontrib>Maiyuran, Subramaniam</creatorcontrib><creatorcontrib>Janus, Scott</creatorcontrib><title>DATA PREFETCHING FOR GRAPHICS DATA PROCESSING</title><description>Embodiments are generally directed to data prefetching for graphics data processing. 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An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the Li cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS |
| title | DATA PREFETCHING FOR GRAPHICS DATA PROCESSING |
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