ENGINEERING CHANGE ORDER (ECO) SPARE CELL
A chip includes a spare cell including a first active region, and a first gate extending over the first active region in a first direction. The chip also includes a tie cell including a second active region, a second gate extending over the second active region in the first direction, a first drain...
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| creator | MEDISETTI, Kamesh VANG, Foua ALAM, Akhtar KANG, Seung Hyuk LIM, Hyeokjin MEHROTRA, Ankur CHANDRANAIKA, Manjanaika BOYNAPALLI, Venugopal HIREMATH, Renukprasad |
| description | A chip includes a spare cell including a first active region, and a first gate extending over the first active region in a first direction. The chip also includes a tie cell including a second active region, a second gate extending over the second active region in the first direction, a first drain contact formed over the second active region, a first source contact formed over the second active region, wherein the second gate is between the first drain contact and the first source contact, and first source contact is coupled to a first rail, and a circuit configured to couple the second gate to a second rail. The chip also includes a metal routing extending in a second direction, wherein the second direction is perpendicular to the first direction, and the first metal routing is coupled to the first drain contact and the first gate. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024249056A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024249056A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024249056A13</originalsourceid><addsrcrecordid>eNrjZNB09XP39HN1DfL0c1dw9nD0c3dV8A9ycQ1S0HB19tdUCA5wDHJVcHb18eFhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRiZGJpYGpmaOhsbEqQIAf4EkuA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ENGINEERING CHANGE ORDER (ECO) SPARE CELL</title><source>esp@cenet</source><creator>MEDISETTI, Kamesh ; VANG, Foua ; ALAM, Akhtar ; KANG, Seung Hyuk ; LIM, Hyeokjin ; MEHROTRA, Ankur ; CHANDRANAIKA, Manjanaika ; BOYNAPALLI, Venugopal ; HIREMATH, Renukprasad</creator><creatorcontrib>MEDISETTI, Kamesh ; VANG, Foua ; ALAM, Akhtar ; KANG, Seung Hyuk ; LIM, Hyeokjin ; MEHROTRA, Ankur ; CHANDRANAIKA, Manjanaika ; BOYNAPALLI, Venugopal ; HIREMATH, Renukprasad</creatorcontrib><description>A chip includes a spare cell including a first active region, and a first gate extending over the first active region in a first direction. The chip also includes a tie cell including a second active region, a second gate extending over the second active region in the first direction, a first drain contact formed over the second active region, a first source contact formed over the second active region, wherein the second gate is between the first drain contact and the first source contact, and first source contact is coupled to a first rail, and a circuit configured to couple the second gate to a second rail. The chip also includes a metal routing extending in a second direction, wherein the second direction is perpendicular to the first direction, and the first metal routing is coupled to the first drain contact and the first gate.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240725&DB=EPODOC&CC=US&NR=2024249056A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240725&DB=EPODOC&CC=US&NR=2024249056A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MEDISETTI, Kamesh</creatorcontrib><creatorcontrib>VANG, Foua</creatorcontrib><creatorcontrib>ALAM, Akhtar</creatorcontrib><creatorcontrib>KANG, Seung Hyuk</creatorcontrib><creatorcontrib>LIM, Hyeokjin</creatorcontrib><creatorcontrib>MEHROTRA, Ankur</creatorcontrib><creatorcontrib>CHANDRANAIKA, Manjanaika</creatorcontrib><creatorcontrib>BOYNAPALLI, Venugopal</creatorcontrib><creatorcontrib>HIREMATH, Renukprasad</creatorcontrib><title>ENGINEERING CHANGE ORDER (ECO) SPARE CELL</title><description>A chip includes a spare cell including a first active region, and a first gate extending over the first active region in a first direction. The chip also includes a tie cell including a second active region, a second gate extending over the second active region in the first direction, a first drain contact formed over the second active region, a first source contact formed over the second active region, wherein the second gate is between the first drain contact and the first source contact, and first source contact is coupled to a first rail, and a circuit configured to couple the second gate to a second rail. The chip also includes a metal routing extending in a second direction, wherein the second direction is perpendicular to the first direction, and the first metal routing is coupled to the first drain contact and the first gate.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNB09XP39HN1DfL0c1dw9nD0c3dV8A9ycQ1S0HB19tdUCA5wDHJVcHb18eFhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRiZGJpYGpmaOhsbEqQIAf4EkuA</recordid><startdate>20240725</startdate><enddate>20240725</enddate><creator>MEDISETTI, Kamesh</creator><creator>VANG, Foua</creator><creator>ALAM, Akhtar</creator><creator>KANG, Seung Hyuk</creator><creator>LIM, Hyeokjin</creator><creator>MEHROTRA, Ankur</creator><creator>CHANDRANAIKA, Manjanaika</creator><creator>BOYNAPALLI, Venugopal</creator><creator>HIREMATH, Renukprasad</creator><scope>EVB</scope></search><sort><creationdate>20240725</creationdate><title>ENGINEERING CHANGE ORDER (ECO) SPARE CELL</title><author>MEDISETTI, Kamesh ; VANG, Foua ; ALAM, Akhtar ; KANG, Seung Hyuk ; LIM, Hyeokjin ; MEHROTRA, Ankur ; CHANDRANAIKA, Manjanaika ; BOYNAPALLI, Venugopal ; HIREMATH, Renukprasad</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024249056A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MEDISETTI, Kamesh</creatorcontrib><creatorcontrib>VANG, Foua</creatorcontrib><creatorcontrib>ALAM, Akhtar</creatorcontrib><creatorcontrib>KANG, Seung Hyuk</creatorcontrib><creatorcontrib>LIM, Hyeokjin</creatorcontrib><creatorcontrib>MEHROTRA, Ankur</creatorcontrib><creatorcontrib>CHANDRANAIKA, Manjanaika</creatorcontrib><creatorcontrib>BOYNAPALLI, Venugopal</creatorcontrib><creatorcontrib>HIREMATH, Renukprasad</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MEDISETTI, Kamesh</au><au>VANG, Foua</au><au>ALAM, Akhtar</au><au>KANG, Seung Hyuk</au><au>LIM, Hyeokjin</au><au>MEHROTRA, Ankur</au><au>CHANDRANAIKA, Manjanaika</au><au>BOYNAPALLI, Venugopal</au><au>HIREMATH, Renukprasad</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ENGINEERING CHANGE ORDER (ECO) SPARE CELL</title><date>2024-07-25</date><risdate>2024</risdate><abstract>A chip includes a spare cell including a first active region, and a first gate extending over the first active region in a first direction. The chip also includes a tie cell including a second active region, a second gate extending over the second active region in the first direction, a first drain contact formed over the second active region, a first source contact formed over the second active region, wherein the second gate is between the first drain contact and the first source contact, and first source contact is coupled to a first rail, and a circuit configured to couple the second gate to a second rail. The chip also includes a metal routing extending in a second direction, wherein the second direction is perpendicular to the first direction, and the first metal routing is coupled to the first drain contact and the first gate.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES |
| title | ENGINEERING CHANGE ORDER (ECO) SPARE CELL |
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