Power Management of a Power Regulator in a Processor During High Current Events

Methods are described for enabling clock waveform synthesis for, in one embodiment, tensor processors, that enable more efficient power management, shorter runtime latency, higher computational job throughput, and a lower implementation cost than alternative clock waveform methods. Further embodiments describe modifications to power regulators to enable programmatic control of power management. This Abstract and the independent Claims are concise signifiers of embodiments of the claimed inventions. The Abstract does not limit the scope of the claimed inventions.