SEMICONDUCTOR MEMORY DEVICE AND ERASE OPERATION METHOD THEREOF

Disclosed is an erase operation method of a semiconductor memory device which includes a cell string disposed between a bit line and a common source line and connected with a plurality of word lines. The operation method includes precharging a channel of the cell string by applying a ground voltage to the bit line and applying a pass voltage to the word lines, and generating a gate induced drain current (GIDL) current by applying an erase voltage to the bit line and the pass voltage to the word lines, and the pass voltage is greater than the ground voltage, and the erase voltage is greater than the pass voltage.