MEMORY DEVICE
A memory device of embodiments includes a memory cell including: a first conductive layer; a second conductive layer; a third conductive layer provided between the first conductive layer and the second conductive layer; a variable resistance layer provided between the first conductive layer and the...
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| creator | NOMOTO, Rina CHOKAWA, Kenta GOTO, Masakazu DAIBOU, Tadaomi KOMATSU, Katsuyoshi KAWAI, Hiroki IWASAKI, Takeshi MATSUSHIMA, Yosuke ONIZAKI, Makoto QI, Zhu |
| description | A memory device of embodiments includes a memory cell including: a first conductive layer; a second conductive layer; a third conductive layer provided between the first conductive layer and the second conductive layer; a variable resistance layer provided between the first conductive layer and the third conductive layer; and a switching layer provided between the third conductive layer and the second conductive layer. The switching layer contains an oxide of a first element, which is at least one element selected from a group consisting of zirconium, yttrium, tantalum, lanthanum, cerium, titanium, hafnium, and magnesium, and a compound of a second element that is at least one element selected from a group consisting of zinc, tin, gallium, indium, and bismuth and a third element that is at least one element selected from a group consisting of tellurium, sulfur, and selenium. |
| format | Patent |
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The switching layer contains an oxide of a first element, which is at least one element selected from a group consisting of zirconium, yttrium, tantalum, lanthanum, cerium, titanium, hafnium, and magnesium, and a compound of a second element that is at least one element selected from a group consisting of zinc, tin, gallium, indium, and bismuth and a third element that is at least one element selected from a group consisting of tellurium, sulfur, and selenium.</description><language>eng</language><subject>ELECTRICITY</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240627&DB=EPODOC&CC=US&NR=2024215459A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240627&DB=EPODOC&CC=US&NR=2024215459A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NOMOTO, Rina</creatorcontrib><creatorcontrib>CHOKAWA, Kenta</creatorcontrib><creatorcontrib>GOTO, Masakazu</creatorcontrib><creatorcontrib>DAIBOU, Tadaomi</creatorcontrib><creatorcontrib>KOMATSU, Katsuyoshi</creatorcontrib><creatorcontrib>KAWAI, Hiroki</creatorcontrib><creatorcontrib>IWASAKI, Takeshi</creatorcontrib><creatorcontrib>MATSUSHIMA, Yosuke</creatorcontrib><creatorcontrib>ONIZAKI, Makoto</creatorcontrib><creatorcontrib>QI, Zhu</creatorcontrib><title>MEMORY DEVICE</title><description>A memory device of embodiments includes a memory cell including: a first conductive layer; a second conductive layer; a third conductive layer provided between the first conductive layer and the second conductive layer; a variable resistance layer provided between the first conductive layer and the third conductive layer; and a switching layer provided between the third conductive layer and the second conductive layer. The switching layer contains an oxide of a first element, which is at least one element selected from a group consisting of zirconium, yttrium, tantalum, lanthanum, cerium, titanium, hafnium, and magnesium, and a compound of a second element that is at least one element selected from a group consisting of zinc, tin, gallium, indium, and bismuth and a third element that is at least one element selected from a group consisting of tellurium, sulfur, and selenium.</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOD1dfX1D4pUcHEN83R25WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGJkaGpiamlo6GxsSpAgAcox2V</recordid><startdate>20240627</startdate><enddate>20240627</enddate><creator>NOMOTO, Rina</creator><creator>CHOKAWA, Kenta</creator><creator>GOTO, Masakazu</creator><creator>DAIBOU, Tadaomi</creator><creator>KOMATSU, Katsuyoshi</creator><creator>KAWAI, Hiroki</creator><creator>IWASAKI, Takeshi</creator><creator>MATSUSHIMA, Yosuke</creator><creator>ONIZAKI, Makoto</creator><creator>QI, Zhu</creator><scope>EVB</scope></search><sort><creationdate>20240627</creationdate><title>MEMORY DEVICE</title><author>NOMOTO, Rina ; CHOKAWA, Kenta ; GOTO, Masakazu ; DAIBOU, Tadaomi ; KOMATSU, Katsuyoshi ; KAWAI, Hiroki ; IWASAKI, Takeshi ; MATSUSHIMA, Yosuke ; ONIZAKI, Makoto ; QI, Zhu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024215459A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>NOMOTO, Rina</creatorcontrib><creatorcontrib>CHOKAWA, Kenta</creatorcontrib><creatorcontrib>GOTO, Masakazu</creatorcontrib><creatorcontrib>DAIBOU, Tadaomi</creatorcontrib><creatorcontrib>KOMATSU, Katsuyoshi</creatorcontrib><creatorcontrib>KAWAI, Hiroki</creatorcontrib><creatorcontrib>IWASAKI, Takeshi</creatorcontrib><creatorcontrib>MATSUSHIMA, Yosuke</creatorcontrib><creatorcontrib>ONIZAKI, Makoto</creatorcontrib><creatorcontrib>QI, Zhu</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NOMOTO, Rina</au><au>CHOKAWA, Kenta</au><au>GOTO, Masakazu</au><au>DAIBOU, Tadaomi</au><au>KOMATSU, Katsuyoshi</au><au>KAWAI, Hiroki</au><au>IWASAKI, Takeshi</au><au>MATSUSHIMA, Yosuke</au><au>ONIZAKI, Makoto</au><au>QI, Zhu</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MEMORY DEVICE</title><date>2024-06-27</date><risdate>2024</risdate><abstract>A memory device of embodiments includes a memory cell including: a first conductive layer; a second conductive layer; a third conductive layer provided between the first conductive layer and the second conductive layer; a variable resistance layer provided between the first conductive layer and the third conductive layer; and a switching layer provided between the third conductive layer and the second conductive layer. The switching layer contains an oxide of a first element, which is at least one element selected from a group consisting of zirconium, yttrium, tantalum, lanthanum, cerium, titanium, hafnium, and magnesium, and a compound of a second element that is at least one element selected from a group consisting of zinc, tin, gallium, indium, and bismuth and a third element that is at least one element selected from a group consisting of tellurium, sulfur, and selenium.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | ELECTRICITY |
| title | MEMORY DEVICE |
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