IC With Delay-Locked Loop With Widened Lock Range

An integrated circuit (IC) features a delay-locked loop (DLL) with a DLL signal input. The DLL comprises a delay line with multiple delay stages, a gater with clock input, and a phase-frequency detector (PFD). The delay line's signal input is linked to the DLL signal input, while the gater'...

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Bibliographische Detailangaben
Hauptverfasser:	SHIN, Jinuk, RAHMAN, Fahim ur
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRICITY IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS RESONATORS
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Beschreibung
Zusammenfassung:	An integrated circuit (IC) features a delay-locked loop (DLL) with a DLL signal input. The DLL comprises a delay line with multiple delay stages, a gater with clock input, and a phase-frequency detector (PFD). The delay line's signal input is linked to the DLL signal input, while the gater's inputs are connected to phase outputs of the delay line. The gater's clock input is tied to the DLL signal input, and its outputs feed into the PFD inputs. The PFD generates outputs that are used by a loop filter to control the speed of the delay line.